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PRELIMINARY PRODUCT INFORMATION
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
V850ES/SA2 , V850ES/SA3 32-BIT SINGLE-CHIP MICROCONTROLLERS
TM TM
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD703201, 703201Y, 70F3201, and 70F3201Y (V850ES/SA2), PD703204, 703204Y, 70F3204, and 70F3204Y (V850ES/SA3) are products in the V850 Family DMA controller. In addition to their high real-time responsiveness and one-clock-pitch execution of instructions, the V850ES/SA2 and V850ES/SA3 include instructions suited to digital servo control applications such as multiplication instructions executed via a hardware multiplier, saturation instructions, and bit manipulation instructions. As a real-time control system, this device provides a high-level cost performance ideal for ultra-low-power DVC and portable audio applications. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. V850ES/SA2, V850ES/SA3 User's Manual Hardware: To be prepared V850ES User's Manual Architecture: To be prepared
TM
of 32-bit single-chip microcontrollers, and include
peripheral functions such as ROM/RAM, timer/counters, serial interfaces, an A/D converter, a D/A converter, and a
FEATURES
Number of instructions: 83 Minimum instruction execution time: 59 ns (@ 17 MHz operation with main system clock (fXX)) 74 ns (@ 13.5 MHz operation with main system clock (fXX)) General-purpose registers: 32 bits x 32 registers Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions Memory space: 64 MB linear address space Memory block division function: 2 MB, 2 MB, 4 MB, 8 MB = Total four blocks External bus interface: 16-bit data bus Address bus: Separate output enabled Internal memory Mask ROM: 256 KB (PD703201, 703201Y, 703204, 703204Y) Flash memory: 256 KB (PD70F3201, 70F3201Y, 70F3204, 70F3204Y) RAM: 16 KB
The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U15436EJ1V0PM00 (1st edition) Date Published June 2001 N CP(K) Printed in Japan
Interrupts and exceptions Non-maskable interrupts: 2 sources Maskable interrupts: 38 sources (PD703201, 70F3201) 39 sources (PD703201Y, 70F3201Y) 39 sources (PD703204, 70F3204) 40 sources (PD703204Y, 70F3204Y) Software exceptions: 32 sources Exception trap: 1 source I/O lines Total: 82 (V850ES/SA2) 102 (V850ES/SA3) Timer/counters 16-bit timer: 2 channels 8-bit timer: 4 channels Real-time counter (for watch): 1 channel Watchdog timer: 1 channel
(c)
2001
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Serial interface (SIO) Asynchronous serial interface (UART): 2 channels Clocked serial interface (CSI): 4 channels (V850ES/SA2), 5 channels (V850ES/SA3) I C bus interface: 1 channel (PD703201Y, 703204Y, 70F3201Y, 70F3204Y) A/D converter: 10-bit resolution x 12 channels (V850ES/SA2) 10-bit resolution x 16 channels (V850ES/SA3)
2
D/A converter: 8-bit resolution x 2 channels DMA controller: 4 channels Power save functions: HALT/IDLE/STOP/Backup modes ROM correction: Four points can be corrected Packages: 100-pin plastic LQFP (14 x 14) (V850ES/SA2) 121-pin plastic FBGA (12 x 12) (V850ES/SA3)
APPLICATIONS
Low-power portable devices DVCs, portable audios
ORDERING INFORMATION
Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 121-pin plastic FBGA (12 x 12) 121-pin plastic FBGA (12 x 12) 100-pin plastic LQFP (fine pitch) (14 x 14) 100-pin plastic LQFP (fine pitch) (14 x 14) 121-pin plastic FBGA (12 x 12) 121-pin plastic FBGA (12 x 12) Internal ROM 256 KB (mask ROM) 256 KB (mask ROM) 256 KB (mask ROM) 256 KB (mask ROM) 256 KB (flash memory) 256 KB (flash memory) 256 KB (flash memory) 256 KB (flash memory)
PD703201GC-xxx-8EU PD703201YGC-xxx-8EU PD703204F1-xxx-EA6 PD703204YF1-xxx-EA6 PD70F3201GC-8EU PD70F3201YGC-8EU PD70F3204F1-EA6 PD70F3204YF1-EA6
Remark
xxx indicates ROM code suffix.
2
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
PIN CONFIGURATION
* V850ES/SA2 100-pin plastic LQFP (fine-pitch) (14 x 14)
PD703201GC-xxx-8EU PD703201YGC-xxx-8EU PD70F3201GC-8EU PD70F3201YGC-8EU
AVREF0 AVDD AVSS P80/ANO0 P81/ANO1 AVREF1 P00/NMI P30/SI1/RXD0 P31/SO1/TXD0 P32/SCK1 VDD VSS X1 X2 RESET XT1 XT2 VSSBU VDDBU P90/A0 P91/A1 P92/A2/INTP5 P93/A3/INTP6 P94/A4/TO2 P95/A5/TO3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 P710/ANI10 P711/ANI11 P05/INTP4 P04/INTP3/TI5 P03/INTP2/TI4 P02/INTP1/TI3 P01/INTP0/TI2 P46/INTP11/TO1 P45/INTP10/TI1/TCLR1 P44/INTP01/TO0 P43/INTP00/TI0/TCLR0 P42/SCK0/SCLNote 1 P41/SO0/SDANote 1 P40/SI0 PDH5/A21
PDH4/A20 PDH3/A19 PDH2/A18 PDH1/A17 PDH0/A16 PDL15/AD15 PDL14/AD14 PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 EVDD EVSS IC/FLMD0Notes 2, 3 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5/FLMD1Note 2 PDL4/AD4 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 PCT7
Notes 1. SCL and SDA are valid only for the PD703201Y and 70F3201Y. 2. FLMD0 and FLMD1 are valid only for the PD70F3201 and 70F3201Y. 3. IC: Connect directly to VSS (PD703201, 703201Y). FLMD0: Connect to VSS in normal mode (PD70F3201, 70F3201Y).
P96/A6/TO4 P97/A7/TO5 P98/A8/RXD1 P99/A9/TXD1 P910/A10/SI2 P911/A11/SO2 P912/A12/SCK2 P913/A13/SI3 P914/A14/SO3 P915/A15/SCK3 EVSS EVDD PCS0/CS0 PCS1/CS1 PCS2/CS2 PCS3/CS3 PCM0/WAIT PCM1/CLKOUT PCM2/HLDAK PCM3/HLDRQ PCT0/WR0 PCT1/WR1 PCT4/RD PCT5 PCT6/ASTB
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Preliminary Product Information U15436EJ1V0PM
3
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
* V850ES/SA3 121-pin plastic FBGA (12 x 12)
PD703204F1-xxx-EA6 PD703204YF1-xxx-EA6
PD70F3204F1-EA6 PD70F3204YF1-EA6
(1/2)
Top View 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGHJKLMN
Bottom View
NMLKJHGFEDCBA
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7
Pin Name P70/ANI0 P71/ANI1 P73/ANI3 P713/ANI13 P76/ANI6 P78/ANI8 P711/ANI11 P04/INTP3/TI5 PCD2 P45/INTP10/TI1/TCLR1 P43/INTP00/TI0/TCLR0 P41/SO0/SDA PDH5/A21 AVDD AVREF0 P72/ANI2 P712/ANI12 P75/ANI5 P77/ANI7 P710/ANI10
Note
Pin No. B8 B9 B10 B11 B12 B13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 PCD3
Pin Name
Pin No. D2 D3 D11 D12 D13 E1 E2 E3 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3 AVREF1
Pin Name
P02/INTP1/TI3 P46/INTP11/TO1 P42/SCK0/SCL P40/SI0 PDH4/A20 P80/ANO0 AVSS P74/ANI4 P714/ANI14 P715/ANI15 P79/ANI9 P05/INTP4 P03/INTP2/TI4 PCD1 P01/INTP0/TI2 P44/INTP01/TO0 PDH3/A19 PDH7/A23 P81/ANO1
Note
P00/NMI PDH0/A16 PDH2/A18 PDH1/A17 P30/SI1/RXD0 P31/SO1/TXD0 P32/SCK1 PDL14/AD14 PDH6/A22 PDL15/AD15 VSS X1 VDD PDL11/AD11 PDL13/AD13 PDL12/AD12 RESET XT1 X2
Note SCL and SDA are valid only for PD703204Y and 70F3204Y. Remark Connect the D4 pin directly to VSS.
4
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2/2)
Pin No. G11 G12 G13 H1 H2 H3 H11 H12 H13 J1 J2 J3 J11 J12 J13 K1 K2 K3 K11 K12 EVSS PDL10/AD10 EVDD VSSBU VDDBU XT2 PDL8/AD8 IC/FLMD0
Notes 1, 2
Pin Name
Pin No. K13 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
Note 1
Pin Name PDL3/AD3 P93/A3/INTP6 P94/A4/TO2 P911/A11/SO2 P914/A14/SO3 P915/A15/SCK3 EVDD PCS0/CS0 PCS2/CS2 PCM4 PCT2 PCT0/WR0 PDL1/AD1 PDL2/AD2 P95/A5/TO3 P97/A7/TO5 P99/A9/TXD1 P913/A13/SI3 EVSS PCS5
Pin No. M7 M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 PCS4
Pin Name
PCM0/WAIT PCM2/HLDAK PCT3 PCT4/RD PCT7 PDL0/AD0 P96/A6/TO4 P98/A8/RXD1 P910/A10/SI2 P912/A12/SCK2 PCS7 PCS6 PCS1/CS1 PCS3/CS3 PCM5 PCM3/HLDRQ PCT1/WR1 PCT5 PCT6/ASTB
PDL9/AD9 P20/SI4 P91/A1 P90/A0 PDL5/AD5/FLMD1 PDL7/AD7 PDL6/AD6 P22/SCK4 P92/A2/INTP5 P21/SO4 PCM1/CLKOUT PDL4/AD4
L12 L13 M1 M2 M3 M4 M5 M6
Notes 1. FLMD0 and FLMD1 are valid only for PD70F3204Y and 70F3204Y. 2. IC: Connect directly to VSS (PD703204, 703204Y). FLMD0: Connect to VSS in normal mode (PD70F3204, 70F3204Y).
Preliminary Product Information U15436EJ1V0PM
5
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
PIN IDENTIFICATION
A0 to A23: AD0 to AD15: ADTRG: ANI0 to ANI15: ANO0, ANO1: ASTB: AVDD: AVREF0, AVREF1: AVSS: CLKOUT: CS0 to CS3: EVDD: EVSS: FLMD0, FLMD1: HLDAK: HLDRQ: IC: INTP0 to INTP6: INTP00, INTP01,: INTP10, INTP11 NMI: P00 to P05: P20 to P22: P30 to P32: P40 to P46: P70 to P715: P80, P81: P90 to P915: Non-maskable interrupt request Port 0 Port 2 Port 3 Port 4 Port 7 Port 8 Port 9 Address bus Address/data bus AD trigger input Analog input Analog output Address strobe Analog VDD Analog reference voltage Analog VSS Clock output Chip select Power supply for port Ground for port Flash programming mode Hold acknowledge Hold request Internally connected Interrupt request from peripherals Interrupt request to timer PCD1 to PCD3: PCM0 to PCM5: PCS0 to PCS7: PCT0 to PCT7: PDH0 to PDH7: PDL0 to PDL15: RD: RESET: RXD0, RXD1: SCK0 to SCK4: SCL: SDA: SI0 to SI4: SO0 to SO4: TCLR0, TCLR1: TI0 to TI5: TO0 to TO5: TXD0, TXD1: VDD: VDDBU: VSS: VSSBU: WAIT: WR0: WR1: X1, X2: XT1, XT2: Port CD Port CM Port CS Port CT Port DH Port DL Read Reset Receive data Serial clock Serial clock Serial data Serial input Serial output Timer clear input Timer input Timer output Transmit data Power supply Power supply for backup Ground Ground for backup Wait Write strobe low level data Write strobe high level data Crystal for main clock Crystal for subclock
6
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
INTERNAL BLOCK DIAGRAM
* V850ES/SA2
NMI INTP0 to INTP6 INTP00, INTP01, INTP10, INTP11 TCLR0, TCLR1 TI0, TI1 TO0, TO1
ROM INTC Note 1 PC 32-bit barrel shifter System registers
General-purpose registers 32-bits x 32
CPU Instruction queue Multiplier 16 x 16 32 BCU ALU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 CS0 to CS3 A0 to A21 AD0 to AD15
Timer/counter 16-bit timer: 2 ch
RAM 16 KB
TI2 to TI5 TO2 to TO5
Timer/counter 8-bit timer: 4 ch SIO
ROM correction
DMAC
SO0 to SO3 SI0 to SI3 SCK0 to SCK3 TXD0, TXD1 RXD0, RXD1 SDA SCL
Note 2
CSI: 4 ch Ports D/A converter A/D converter CG
CLKOUT X1 X2 XT1 XT2 RG RESET ICNote 3 FLMD0Note 4, FLMD1Note 4 VDD VSS VDDBU VSSBU EVDD EVSS
PCS0 to PCS3 PCM0 to PCM3 PCT0, PCT1, PCT4 to PCT7 PDH0 to PDH5 PDL0 to PDL15 P90 to P915 P80, P81 P70 to P711 P40 to P46 P30 to P32 P00 to P05
UART: 2 ch
I2CNote 2: 1 ch
Note 2
Real-time counter Watchdog timer
Notes 1. PD703201, 703201Y:
256 KB (mask ROM) 256 KB (flash memory)
PD70F3201, 70F3201Y:
2. Applies to the PD703201Y and 70F3201Y only. 3. Applies to the PD703201 and 703201Y only. 4. Applies to the PD70F3201 and 70F3201Y only.
AVDD AVREF0 AVSS ANI0 to ANI11
ANO0, ANO1 AVREF1
Preliminary Product Information U15436EJ1V0PM
7
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
* V850ES/SA3
NMI INTP0 to INTP6 INTP00, INTP01, INTP10, INTP11 TCLR0, TCLR1 TI0, TI1 TO0, TO1
ROM INTC Note 1 PC 32-bit barrel shifter System registers
General-purpose registers 32-bits x 32
CPU Instruction queue Multiplier 16 x 16 32 BCU ALU HLDRQ HLDAK ASTB RD WAIT WR0, WR1 CS0 to CS3 A0 to A23 AD0 to AD15
Timer/counter 16-bit timer: 2 ch
RAM 16 KB
TI2 to TI5 TO2 to TO5
Timer/counter 8-bit timer: 4 ch SIO
ROM correction
DMAC
SO0 to SO4 SI0 to SI4 SCK0 to SCK4 TXD0, TXD1 RXD0, RXD1 SDANote 2 SCL
Note 2
CSI: 5 ch Ports D/A converter A/D converter CG
CLKOUT X1 X2 XT1 XT2 RG RESET ICNote 3 FLMD0Note 4, FLMD1Note 4 VDD VSS VDDBU VSSBU EVDD EVSS
PCS0 to PCS7 PCM0 to PCM5 PCT0 to PCT7 PDH0 to PDH7 PDL0 to PDL15 PCD1 to PCD3 P90 to P915 P80, P81 P70 to P715 P40 to P46 P30 to P32 P20 to P22 P00 to P05
UART: 2 ch
I2CNote 2:1 ch
Real-time counter Watchdog timer
Notes 1. PD703204, 703204Y:
256 KB (mask ROM)
PD70F3204, 70F3204Y: 256 KB (flash memory)
2. Applies to the PD703204Y and 70F3204Y only. 3. Applies to the PD703204 and 703204Y only. 4. Applies to the PD70F3204 and 70F3204Y only.
8
Preliminary Product Information U15436EJ1V0PM
AVDD AVREF0 AVSS ANI0 to ANI15
ANO0, ANO1 AVREF1
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
CONTENTS
1.
PIN FUNCTIONS ................................................................................................................................11
1.1 1.2 1.3 Port Pins ................................................................................................................................................... 11 Non-Port Pins........................................................................................................................................... 14 Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 18
2.
FUNCTION BLOCKS .........................................................................................................................22
2.1 Internal Units............................................................................................................................................ 22
3. 4. 5. 6. 7. 8. 9.
CPU FUNCTIONS................................................................................................................................25 MEMORY MAP ...................................................................................................................................26 EXTERNAL BUS INTERFACE FUNCTION.....................................................................................28 INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION ..............................................31 CLOCK GENERATION FUNCTION..................................................................................................34 POWER SAVE FUNCTION ...............................................................................................................35 TIMER/COUNTER FUNCTION...........................................................................................................37
10. REAL-TIME COUNTER FUNCTION .................................................................................................40 11. WATCHDOG TIMER FUNCTION......................................................................................................41 12. SERIAL INTERFACE FUNCTION.....................................................................................................42
12.1 3-Wire Serial I/O (CSIn)............................................................................................................................ 42 12.2 Asynchronous Serial Interface (UART0 and UART1) ........................................................................... 44 12.3 I C Bus (I C) (PD703201Y, 703204Y, 70F3201Y, 70F3204Y) ................................................................ 45
2 2
13. A/D CONVERTER...............................................................................................................................46 14. D/A CONVERTER...............................................................................................................................48 15. DMA FUNCTION.................................................................................................................................49 16. ROM CORRECTION FUNCTION ......................................................................................................50 17. RESET FUNCTION.............................................................................................................................51 18. FLASH MEMORY (PD70F3201, 70F3201Y, 70F3204, 70F3204Y) ............................................52 19. INSTRUCTION SET LIST..................................................................................................................54
19.1 Conventions ............................................................................................................................................. 54
Preliminary Product Information U15436EJ1V0PM
9
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
19.2 Instruction Set (In Alphabetical Order) ..................................................................................................57
20. ELECTRICAL SPECIFICATIONS (TARGET VALUES) ................................................................. 64 21. PACKAGE DRAWINGS..................................................................................................................... 92 APPENDIX DEVELOPMENT TOOLS ..................................................................................................... 94
10
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
1. PIN FUNCTIONS 1.1 Port Pins
(1/3)
Pin Name P00 P01 P02 P03 P04 P05 [P20] [P21] [P22] P30 P31 P32 P40 P41 P42 P43 P44 P45 P46 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P710 P711 [P712] [P713] [P714] [P715] Input No Port 7 12-bit input port (V850ES/SA2) 16-bit input port (V850ES/SA3) I/O Yes I/O Yes I/O Yes Port 2 3-bit I/O port Input/output can be specified in 1-bit units. N-ch open drain can be specified in 1-bit units (P21, P22 only). Port 3 3-bit I/O port Input/output can be specified in 1-bit units. N-ch open drain can be specified in 1-bit units (P31, P32 only). Port 4 7-bit I/O port Input/output can be specified in 1-bit units. N-ch open drain can be specified in 1-bit units (P41, P42 only). I/O I/O PULL Yes Function Port 0 6-bit I/O port Input/output can be specified in 1-bit units. Alternate Function NMI INTP0/TI2 INTP1/TI3 INTP2/TI4 INTP3/TI5 INTP4 [SI4] [SO4] [SCK4] SI1/RXD0 SO1/TXD0 SCK1 SI0 SO0/SDANote SCK0/SCLNote INTP00/TI0/TCLR0 INTP01/TO0 INTP10/TI1/TCLR1 INTP11/TO1 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 [ANI12] [ANI13] [ANI14] [ANI15]
Note Applies to the PD703201Y, 703204Y, 70F3201Y, and 70F3204Y only. Remarks 1. PULL: On-chip pull-up resistor 2. Pins in brackets ([ ]) are only for the V850ES/SA3.
Preliminary Product Information U15436EJ1V0PM
11
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2/3)
Pin Name P80 P81 P90 P91 P92 P93 P94 P95 P96 P97 P98 P99 P910 P911 P912 P913 P914 P915 [PCD1] [PCD2] [PCD3] PCM0 PCM1 PCM2 PCM3 [PCM4] [PCM5] PCS0 PCS1 PCS2 PCS3 [PCS4] [PCS5] [PCS6] [PCS7] I/O No Port 10 4-bit I/O port (V850ES/SA2) 8-bit I/O port (V850ES/SA3) Input/output can be specified in 1-bit units. CS0 CS1 CS2 CS3 - - - - I/O No 4-bit I/O port (V850ES/SA2) 6-bit I/O port (V850ES/SA3) Input/output can be specified in 1-bit units. WAIT CLKOUT HLDAK HLDRQ - - I/O No Port CD 3-bit I/O port Input/output can be specified in 1-bit units. I/O Yes I/O Input PULL No Port 8 2-bit input port Port 9 16-bit I/O port Input/output can be specified in 1-bit units. N-ch open drain can be specified in 1-bit units (P911, P912, P914, P915 only). Function Alternate Function ANO0 ANO1 A0 A1 A2/INTP5 A3/INTP6 A4/TO2 A5/TO3 A6/TO4 A7/TO5 A8/RXD1 A9/TXD1 A10/SI2 A11/SO2 A12/SCK2 A13/SI3 A14/SO3 A15/SCK3 - - -
Remarks 1. PULL: On-chip pull-up resistor 2. Pins in brackets ([ ]) are only for the V850ES/SA3.
12
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(3/3)
Pin Name PCT0 PCT1 [PCT2] [PCT3] PCT4 PCT5 PCT6 PCT7 PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 [PDH6] [PDH7] PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 I/O No Port DL 16-bit I/O port Input/output can be specified in 1-bit units. I/O No Port DH 6-bit I/O port (V850ES/SA2) 8-bit I/O port (V850ES/SA3) Input/output can be specified in 1-bit units. A16 A17 A18 A19 A20 A21 [A22] [A23] AD0 AD1 AD2 AD3 AD4 AD5/FLMD1Note AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ASTB - RD - I/O I/O PULL No Function Port CT 6-bit I/O port (V850ES/SA2) 8-bit I/O port (V850ES/SA3) Input/output can be specified in 1-bit units. Alternate Function WR0 WR1 - -
Note Applies to the PD70F3201, 70F3201Y, 70F3204, and 70F3204Y only. Remarks 1. PULL: On-chip pull-up resistor 2. Pins in brackets ([ ]) are only for the V850ES/SA3.
Preliminary Product Information U15436EJ1V0PM
13
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
1.2 Non-Port Pins
(1/4)
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 to A21, [A22, A23] AD0 to AD4 AD5 AD6 to AD15 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 [ANI12] [ANI13] [ANI14] [ANI15] Input No Analog voltage input for A/D converter Output I/O No No Address bus for external memory Address/data bus for external memory I/O Output PULL Yes Function Address bus for external memory (when using separate bus) Alternate Function P90 P91 P92/INTP5 P93/INTP6 P94/TO2 P95/TO3 P96/TO4 P97/TO5 P98/RXD1 P99/TXD1 P910/SI2 P911/SO2 P912/SCK2 P913/SI3 P914/SO3 P915/SCK3 PDH0 to PDH5, [PDH6, PDH7] PDL0 to PDL4 PDL5/FLMD1Note PDL6 to PDL15 P70 P71 P72 P73 P74 P75 P76 P77 P78 P79 P710 P711 [P712] [P713] [P714] [P715]
Note Applies to the PD70F3201, 70F3201Y, 70F3204, and 70F3204Y only. Remarks 1. PULL: On-chip pull-up resistor 2. Pins in brackets ([ ]) are only for the V850ES/SA3.
14
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2/4)
Pin Name ANO0 ANO1 ASTB AVDD AVREF0 AVREF1 AVSS CLKOUT CS0 to CS3 EVDD EVSS FLMD0 FLMD1
Note 1
I/O Output
PULL No
Function Analog voltage output for D/A converter
Alternate Function P80 P81
Output - Input
No - -
Address strobe signal output for external memory Positive power supply for A/D converter (same potential as VDD) Reference voltage input for A/D converter Reference voltage input for D/A converter
PCT6 - - - - PCM1 PCS0 to PCS3 - - - PDL5/AD5
- Output Output - - Input
- No No - - No
Ground potential for A/D, D/A converters (same potential as VSS) Internal system clock output Chip select output Positive power supply for external devices (same potential as VDD) Ground potential for external devices (same potential as VSS) Flash programming mode lead-in pins
Note 1
HLDAK HLDRQ IC INTP0 to INTP3 INTP4 INTP5 INTP6 INTP00 INTP01 INTP10 INTP11 NMI RD RESET RXD0 RXD1 SCK0 SCK1 SCK2 SCK3 [SCK4] SCL
Note 2
Output Input - Input
No No - Yes
Bus hold acknowledge output Bus hold request input Internally connected (directly connect to VSS). (PD703201, 703201Y, 703204, and 703204Y only) External interrupt request input (maskable, analog noise elimination)
PCM2 PCM3 - P01/TI2 to P04/TI5 P05 P92/A2 P93/A3
Input
Yes
Capture trigger input (TM0)
P43/TI0/TCLR0 P44/TO0
Capture trigger input (TM1)
P45/TI1/TCLR1 P46/TO1
Input Output Input Input
Yes No - Yes
External interrupt input (non-maskable, analog noise elimination) Read strobe signal output for external memory System reset input Serial receive data input (UART0) Serial receive data input (UART1)
P00 PCT4 - P30/SI1 P98/A8 P42/SCLNote 2 P32 P912/A12 P915/A15 [P22] P42/SCK0 P41/SO0
I/O
Yes
Serial clock I/O (CSI0) Serial clock I/O (CSI1) Serial clock I/O (CSI2) Serial clock I/O (CSI3) Serial clock I/O (CSI4)
I/O I/O
Yes Yes
Serial clock I/O (I C) Serial transmit/receive data I/O (I2C)
2
SDANote 2
Notes 1. Applies to the PD70F3201, 70F3201Y, 70F3204, and 70F3204Y only. 2. Applies to the PD703201Y, 703204Y, 70F3201Y, and 70F3204Y only. Remarks 1. PULL: On-chip pull-up resistor 2. Pins in brackets ([ ]) are only for the V850ES/SA3.
Preliminary Product Information U15436EJ1V0PM
15
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(3/4)
Pin Name SI0 SI1 SI2 SI3 [SI4] SO0 SO1 SO2 SO3 [SO4] TCLR0 TCLR1 TI0 TI1 TI2 TI3 TI4 TI5 TO0 TO1 TO2 TO3 TO4 TO5 TXD0 TXD1 VDD - - Output Yes Output Yes Input Yes Input Yes Output Yes I/O Input PULL Yes Function Serial receive data input (CSI0) Serial receive data input (CSI1) Serial receive data input (CSI2) Serial receive data input (CSI3) Serial receive data input (CSI4) Serial transmit data output (CSI0) Serial transmit data output (CSI1) Serial transmit data output (CSI2) Serial transmit data output (CSI3) Serial transmit data output (CSI4) Timer clear input (TM0) Timer clear input (TM1) External event/clock input (TM0) External event/clock input (TM1) External event/clock input (TM2) External event/clock input (TM3) External event/clock input (TM4) External event/clock input (TM5) Timer output (TM0) Timer output (TM1) Timer output (TM2) Timer output (TM3) Timer output (TM4) Timer output (TM5) Serial transmit data output (UART0) Serial transmit data output (UART1) Positive power supply pin for internal functions (except for subclock oscillator, RTC, and internal RAM) Positive power supply pin for backup (for subclock oscillator, RTC and internal RAM) Ground potential for internal functions (except for subclock oscillator, RTC, and internal RAM) Ground potential for backup (for subclock oscillator, RTC and internal RAM) External wait input Write strobe for external memory (lower 8 bits) Write strobe for external memory (higher 8 bits) PCM0 PCT0 PCT1 Alternate Function P40 P30/RXD0 P910/A10 P913/A13 [P20] P41/SDANote P31/TXD0 P911/A11 P914/A14 [P21] P43/INTP00/TI0 P45/INTP10/TI1 P43/INTP00/TCLR0 P45/INTP10/TCLR1 P01/INTP0 P02/INTP1 P03/INTP2 P04/INTP3 P44/INTP01 P46/INTP11 P94/A4 P95/A5 P96/A6 P97/A7 P31/SO1 P99/A9 -
VDDBU
-
-
-
VSS
-
-
-
VSSBU
-
-
-
WAIT WR0 WR1
Input Output
No No
Note Applies to the PD703201Y, 703204Y, 70F3201Y, and 70F3204Y only. Remarks 1. PULL: On-chip pull-up resistor 2. Pins in brackets ([ ]) are only for the V850ES/SA3.
16
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(4/4)
Pin Name X1 X2 XT1 XT2 I/O Input - Input - No Connecting resonator for subclock PULL No Function Connecting resonator for main clock Alternate Function - - - -
Remark
PULL: On-chip pull-up resistor
Preliminary Product Information U15436EJ1V0PM
17
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
1.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are show in Table 1-1. For the schematic circuit diagram of each type, refer to Figure 1-1. Table 1-1. Types of Pin I/O Circuits (1/2)
Pin P00 P01 to P04 P05 [P20] [P21] [P22] P30 P31 P32 P40 P41 P42 P43 P44 P45 P46 P70 to P711, [P712 to P715] P80, P81 P90, P91 P92, P93 P94 to P97 P98 P99 P910 P911 P912 P913 P914 P915 [PCD1 to PCD3] PCM0 PCM1 PCM2 WAIT CLKOUT HLDAK NMI INTP0/TI2 to INTP3/TI5 INTP4 [SI4] [SO4] [SCK4] SI1/RXD0 SO1/TXD0 SCK1 SI0 SO0/SDA
Note
Alternate Function
I/O Circuit Type 5-W
Recommended Connection of Unused Pins Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open.
5-W 10-E 10-F 5-W 10-E 10-F 5-W 10-F 10-F 5-W
SCK0/SCL
Note
INTP00/TI0/TCLR0 INTP01/TO0 INTP10/TI1/TCLR1 INTP11/TO1 ANI0 to ANI15
9
Independently connect to AVDD or AVSS via a resistor.
ANO0, ANO1 A0, A1 A2/INTP5, A3/INTP6 A4/TO2 to A7/TO5 A8/RXD1 A9/TXD1 A10/SI2 A11/SO2 A12/SCK2 A13/SI3 A14/SO3 A15/SCK3 -
34 5-A 5-W 5-A 5-W 5-A 5-W 10-E 10-F 5-W 10-E 10-F 5 Input: Independently connect to EVDD or EVSS via a resistor. Output: Leave open.
Note Applies to the PD703201Y, 703204Y, 70F3201Y, and 70F3204Y only. Remark Pins in brackets ([ ]) are only for the V850ES/SA3.
18
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Table 1-1. Types of Pin I/O Circuits (2/2)
Pin PCM3 [PCM4] [PCM5] PCS0 to PCS3 [PCS4 to PCS7] PCT0, PCT1 [PCT2, PCT3] PCT4 PCT5 PCT6 PCT7 PDH0 to PDH5, [PDH6, PDH7] PDL0 to PDL4 PDL5 PDL6 to PDL15 AVDD AVREF0 AVREF1 AVSS EVDD EVSS FLMD0Note 1 IC
Note 2
Alternate Function HLDRQ - - CS0 to CS3 - WR0, WR1 - RD - ASTB - A16 to A21, [A22, A23]
I/O Circuit Type 5 Input:
Recommended Connection of Unused Pins Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
AD0 to AD4 AD5/FLMD1Note 1 AD6 to AD15 - - - - - - - - - - - - - - - - - - - - - - - - - 2 - - - - - - 16 16 - Connect to AVSS via a resistor. Connect to AVSS via a resistor. - - - - - - - - - - - - Connect to VSSBU via a resistor. Leave open.
RESET VDD VDDBU VSS VSSBU X1 X2 XT1 XT2
Notes 1. Applies to the PD70F3201, 70F3201Y, 70F3204, and 70F3204Y only. 2. Applies to the PD703201, 703201Y, 703204, and 703204Y only. Remark Pins in brackets ([ ]) are only for the V850ES/SA3.
Preliminary Product Information U15436EJ1V0PM
19
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Figure 1-1. Pin I/O Circuits (1/2)
Type 2
Type 5-W
EVDD
Pullup enable Data IN
P-ch EVDD P-ch IN/OUT
Output disable Schmitt-triggered input with hysteresis characteristics Input enable Type 5 EVDD Data P-ch IN/OUT Output disable N-ch P-ch IN N-ch Type 9
N-ch
+ -
Comparator
AVREF0 (threshold voltage)
Input enable
Input enable
Type 5-A
EVDD
Type 10-E Pullup enable EVDD Data IN/OUT P-ch
EVDD
Pullup enable Data
P-ch EVDD P-ch
P-ch
IN/OUT Open drain Output disable N-ch
Output disable Input enable
N-ch
Input enable
20
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Figure 1-1. Pin I/O Circuits (2/2)
Type 10-F
EVDD
Type 34
Pullup enable EVDD Data P-ch
P-ch
P-ch IN/OUT N-ch
IN/OUT
Analog output voltage
Open drain Output disable Input enable N-ch
Input enable
Type 16 Feedback cut-off P-ch
XT1
XT2
Preliminary Product Information U15436EJ1V0PM
21
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
2. FUNCTION BLOCKS 2.1 Internal Units
Each internal unit of the V850ES/SA2 and V850ES/SA3 is described below. (1) CPU The CPU uses five-stage pipeline control to enable 1-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as the multiplier (16 bits x 16 bits 32 bits) and the barrel shifter (32 bits), helps accelerate processing of complex instructions. (2) Bus control unit (BCU) The BCU starts the required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal instruction queue. (3) ROM This consists of a 256 KB mask ROM or flash memory mapped to the address space 0000000H to 003FFFFH. This area can be accessed by the CPU in 1-clock cycle when an instruction is fetched. (4) RAM This consists of a 16 KB RAM mapped to the address space 3FFB000H to 3FFEFFFH. This area can be accessed by the CPU in 1-clock cycle. (5) Interrupt controller (INTC) This controller services hardware interrupt requests (NMI, INTP0 to INTP6) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiple servicing control can be performed for interrupt sources. (6) Clock generator (CG) The clock generator includes two types of oscillators, one for the main clock (fXX) and one for the subclock (fXT), generates five types of clocks (fXX, fXX/2, fXX/4, fXX/8, fXX/16, and fXX/32), and supplies one of them as the operating clock for the CPU (fCPU). The subclock can only be selected as the operation clock of the real-time counter. (7) Timer/counter A two-channel 16-bit timer/event counter and a four-channel 8-bit timer/event counter are incorporated, which enables measurement of pulse intervals and frequency as well as programmable pulse output. Two channels of the 8-bit timer/event counter can be connected via a cascade connection to enable use as a 16-bit timer.
22
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(8) Real-time counter (for watch) This counter counts the reference time period (1 second) for watch counting by using the 32.768 kHz subclock or the main clock. At the same time, the real-time counter can also be used as an interval timer that uses the main clock as a source clock. This counter includes week, date, hour, minute, and second counters, and is capable of counting up to 4,095 weeks. (9) Watchdog timer This timer detects inadvertent program loops, system abnormalities, etc. It can also be used as an interval timer. When used as a watchdog timer, it generates a non-maskable interrupt request (INTWDT) after an overflow occurs. When used as an interval timer, it generates a maskable interrupt request (INTWDTM) after an overflow occurs. (10)Serial interface (SIO) The V850ES/SA2 and V850ES/SA3 incorporate three kinds of serial interfaces: asynchronous serial interfaces (UART0 and UART1), clocked serial interfaces (V850E/SA2: CSI0 to CSI3, V850ES/SA3: CSI0 to CSI4), and an I C bus interface (I C). The V850ES/SA2 is capable of using up to 4 channels and the V850ES/SA3 is capable of using up to 5 channels simultaneously. Among these channels, one channel can be switched between UART and CSI, and other one channel can be switched between CSI and I C. For UART0 and UART1, data is transferred via the TXDO, TXD1, RXD0, and RXD1 pins. For CSI0 to CSI3, data is transferred via the SO0 to SO3, SI0 to SI3, and SCK0 to SCK3 pins. For CSI4, data is transferred via the SO4, SI4, and SCK4 pins (V850ES/SA3 only). For I C, data is transferred via the SDA and SCL pins. I C is incorporated in the PD703201Y, 703204Y, 70F3201Y and 70F3204Y only.
2 2 2 2 2
UART includes an on-chip dedicated baud rate generator. (11)A/D converter This high-speed, high-resolution 10-bit A/D converter includes 12 analog input pins for the V850ES/SA2 and 16 for the V850ES/SA3. Conversion is performed using the successive approximation method. (12)D/A converter A two-channel 8-bit resolution D/A converter is incorporated. This D/A converter uses the R string method. (13)DMA controller A 4-channel DMA controller is incorporated. Data is transferred between internal RAM, on-chip peripheral I/O, and external memory based on interrupt requests by the on-chip peripheral I/O. (14)ROM correction This is a function that replaces a part of the program in the mask ROM with a program in the internal RAM for execution. Four points can be corrected.
Preliminary Product Information U15436EJ1V0PM
23
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(15)Ports The ports function as both general-purpose ports and control pins, as shown below.
Port P0 P2 P3 P4 P7
Note
I/O 6-bit I/O 3-bit I/O 3-bit I/O 7-bit I/O 12-bit input (V850ES/SA2) 16-bit input (V850ES/SA3) 2-bit input 16-bit I/O
Port Function Generalpurpose port
Control Function NMI, external interrupt, timer input Serial interface Serial interface Serial interface, timer I/O, timer trigger A/D converter analog input
P8 P9
D/A converter analog output External address bus, serial interface, timer output, external interrupt - External bus interface
PCDNote PCM
3-bit I/O 4-bit I/O (V850ES/SA2) 6-bit I/O (V850ES/SA3) 4-bit I/O (V850ES/SA2) 8-bit I/O (V850ES/SA3) 6-bit I/O (V850ES/SA2) 8-bit I/O (V850ES/SA3) 6-bit I/O (V850ES/SA2) 8-bit I/O (V850ES/SA3) 16-bit I/O
PCS
Chip select output
PCT
External bus interface
PDH
External address bus
PDL
External address/data bus
Note V850ES/SA3 only
24
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
3. CPU FUNCTIONS
The CPU of the V850ES/SA2 and V850ES/SA3 is based on RISC architecture and executes most instructions in a 1-clock cycle by using a 5-stage pipeline. The features of the CPU are as follows. Minimum instruction execution time: 59 ns (@ 17 MHz operation with main system clock (fXX)) 74 ns (@ 13.5 MHz operation with main system clock (fXX)) Address space: 64 MB linear * Memory block division function: 2 MB, 2 MB, 4 MB, 8 MB = Total four blocks General-purpose registers: 32 bits x 32 Internal 32-bit architecture 5-stage pipeline control Multiplication/division instructions Saturation operation instructions 1-clock 32-bit shift instruction Load/store instructions with long/short format Internal memory * Mask ROM: * RAM: 16 KB Four types of bit manipulation instructions * SET1 * CLR1 * NOT1 * TST1 256 KB (PD703201, 703201Y, 703204, 703204Y) Flash memory: 256 KB (PD70F3201, 70F3201Y, 70F3204, 70F3204Y)
Preliminary Product Information U15436EJ1V0PM
25
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
4. MEMORY MAP
The memory maps of the V850ES/SA2 and V850ES/SA3 are shown below. Address Space
Image 63
4 GB
Data space Peripheral I/O area Image 1
Program space Peripheral I/O area
Internal RAM area Programmable peripheral I/O areaNote or reserved area 64 MB
Internal RAM area
Programmable peripheral I/O area
Reserved area
Reserved area 64 MB Image 0 External memory area
External memory area 16 MB Internal ROM area (external memory area) Internal ROM area (external memory area)
Note The programmable peripheral I/O area in the data space can only be used for image 4n (n = 0 to 15). It cannot be used for other images (reserved area). Remark Internal ROM: 256 KB (0000000H to 003FFFFH) Internal RAM: 16 KB (3FFB000H to 3FFEFFFH)
26
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Data Memory Map
3FFFFFFH (80 KB) 3FEC000H 3FEBFFFH
On-chip peripheral area (4 KB)
3FFFFFFH 3FFF000H 3FFEFFFH
Internal RAM area (16 KB)
Reserved area
3FFB000H 3FFAFFFH Reserved area
1000000H 0FFFFFFH
3FEC000H
External memory areaNote 1 (8 MB)
CS3
0800000H 07FFFFFH
External memory area (4 MB) 0400000H 03FFFFFH External memory area (2 MB) 0200000H 01FFFFFH (2 MB) 0000000H
CS2
01FFFFFH CS1 External memory area (1 MB) Internal ROM areaNote 2 (1 MB) 0000000H
0100000H 00FFFFFH
CS0
Notes 1. In the V850ES/SA2, this area is the 4 MB space of 0800000H to 0BFFFFFH (0C00000H to 0FFFFFFH is an image of 0800000H to 0BFFFFFH). 2. This area is used as an external memory area during data write access.
Preliminary Product Information U15436EJ1V0PM
27
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
5. EXTERNAL BUS INTERFACE FUNCTION
The V850ES/SA2 and V850ES/SA3 incorporate an external bus interface function that can be used to connect memories, such as ROM or RAM, and peripheral I/O externally. The external bus interface function has the following features. Separate bus/multiplexed bus output selectable 8-bit/16-bit data bus sizing function Chip select function for four spaces Wait function * Programmable wait function * External wait function Idle state function Bus hold function The following pins are used for the external bus interface. Table 5-1. List of Bus Control Pins (When Multiplexed Bus Is Selected)
Bus Control Pin AD0 to AD15 A16 to A23 WAIT CLKOUT CS0 to CS3 WR0, WR1 RD ASTB HLDRQ HLDAK
Note
Alternate Function PDL0 to PDL15 PDH0 to PDH7 PCM0 PCM1 PCS0 to PCS3 PCT0, PCT1 PCT4 PCT6 PCM3 PCM2
I/O I/O Output Input Output Output Output Output Output Input Output Address/data bus Address bus External wait control Internal system clock Chip select Write strobe signal Read strobe signal Address strobe signal Bus hold control
Function
Note A16 to A21 in the V850ES/SA2. Table 5-2. List of Bus Control Pins (When Separate Bus Is Selected)
Bus Control Pin AD0 to AD15 A0 to A15 A16 to A23 WAIT CLKOUT CS0 to CS3 WR0, WR1 RD HLDRQ HLDAK
Note
Alternate Function PDL0 to PDL15 P90 to P915 PDH0 to PDH7 PCM0 PCM1 PCS0 to PCS3 PCT0, PCT1 PCT4 PCM3 PCM2
I/O I/O Output Output Input Output Output Output Output Input Output Data bus Address bus Address bus External wait control Internal system clock Chip select Write strobe signal Read strobe signal Bus hold control
Function
Note A16 to A21 in the V850ES/SA2.
28
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
The number of basic clocks required for accessing each area in the address space is as follows. Table 5-3. Number of Access Clocks
Area (Bus Width) Bus Cycle Type Instruction fetch (normal access) Instruction fetch (branch) Operand data access Internal ROM (32 Bits) 1 2 3 Internal RAM (32 Bits) 1 or 2 1 or 2 1 External Memory (16 Bits) 3 + nNote 3 + nNote 3 + nNote
Note 2 + n clocks when the separate bus is selected. n is the number of waits. Figure 5-1. Example of Timing In Separate Bus Mode (Read Write)
T1 CLKOUT (output)
T2
T1
T2
A0 to A23 (output)
Address
Address
RD (output)
WR0, WR1 (output)
AD0 to AD15 (I/O)
Data
Data
WAIT (input)
Remark The broken lines indicates the high-impedance state
Preliminary Product Information U15436EJ1V0PM
29
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Figure 5-2. Example of Timing In Multiplexed Bus Mode (Read Write)
T1 CLKOUT (output)
T2
T3
T1
T2
T3
A0 to A23 (output)
Address
Address
AD0 to AD15 (I/O)
Address
Data
Address
Data
ASTB (output)
WR0, WR1 (output)
RD (output)
WAIT (input)
Remark The broken lines indicate the high-impedance state.
30
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
6. INTERRUPT SERVICING/EXCEPTION PROCESSING FUNCTION
The features of the interrupt servicing/exception processing function are as follows. Interrupt * Non-maskable interrupt: 2 sources * Maskable interrupt
PD703201, 70F3201: PD703204, 70F3204:
External 8, internal 30 sources External 8, internal 31 sources
PD703201Y, 70F3201Y: External 8, internal 31 sources PD703204Y, 70F3204Y: External 8, internal 32 sources
* 8-level programmable priority control * Mask specification for the interrupt request according to priority * Mask specification for each maskable interrupt request * Noise elimination, edge detection, and valid edge specification of an external interrupt request Exceptions * Software exception: 32 sources * Exception trap: 2 sources (illegal op code exception, debug trap) Table 6-1 shows the interrupt/exception sources.
Preliminary Product Information U15436EJ1V0PM
31
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Table 6-1. Interrupt Source List (1/2)
Type Classification Default Priority - - - - - - 0 1 2 3 4 5 6 7 8 9 Name Trigger Genera- Exception ting Unit Code Handler Address Restored PC Interrupt Control Register - - - - - - WDTIC PIC0 PIC1 PIC2 PIC3 PIC4 PIC5 PIC6 RTCIC CCIC00
Reset
Interrupt
RESET
RESET pin input
Pin
0000H
00000000H
Undefined
WDT overflow (WDTRES) WDT NonInterrupt maskable Software Exception exception Exception Exception trap Maskable Interrupt NMI INTWDT TRAP0n TRAP1n ILGOP/ DBG0 INTWDTM INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTRTC INTCC00
Note
NMI pin valid edge input WDT overflow TRAP instruction TRAP instruction Illegal op code/ DBTRAP instruction Internal timer overflow INTP0 pin valid edge input INTP1 pin valid edge input INTP2 pin valid edge input INTP3 pin valid edge input INTP4 pin valid edge input INTP5 pin valid edge input INTP6 pin valid edge input RTC interrupt CC00 capture trigger input/match between TM0 and CC00 CC01 capture trigger input/match between TM0 and CC01 TM0 overflow CC10 capture trigger input/match between TM1 and CC10 CC11 capture trigger input/match between TM1 and CC11 TM1 overflow
- WDT - - - WDT Pin Pin Pin Pin Pin Pin Pin RTC TM0
0010H 0020H 004nH 005nH
Note
00000010H 00000020H 00000040H 00000050H 00000060H 00000080H 00000090H 000000A0H 000000B0H 000000C0H 000000D0H 000000E0H 000000F0H 00000100H 00000110H
nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC
Note
Note
0060H 0080H 0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0100H 0110H
10
INTCC01
TM0
0120H
00000120H
nextPC
CCIC01
11 12
INTOVF0 INTCC10
TM0 TM1
0130H 0140H
00000130H 00000140H
nextPC nextPC
OVFIC0 CCIC10
13
INTCC11
TM1
0150H
00000150H
nextPC
CCIC11
14 15 16
INTOVF1 INTTM2 INTTM3
TM1
0160H 0170H 0180H
00000160H 00000170H 00000180H
nextPC nextPC nextPC
OVFIC1 TMIC2 TMIC3
Match between TM2 and TM2 CR2/TM2 overflow Match between TM3 and TM3 CR3/TM3 overflow
Note n: Value of 0 to FH
32
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Table 6-1. Interrupt Source List (2/2)
Type Classification Default Priority Name Trigger Genera- Exception ting Unit Code Handler Address Restored Interrupt PC Control Register nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC nextPC TMIC4 TMIC5 CSIIC0 IICIC0 CSIIC1 SREIC0 SRIC0 STIC0 CSIIC2 SREIC1 SRIC1 STIC1 CSIIC3 CSIIC4 ADIC DMAIC0 DMAIC1 DMAIC2 DMAIC3 ROVIC BRGIC
Maskable Interrupt
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
INTTM4 INTTM5 INTCSI0 INTIIC
Note 1
Match between TM4 and TM4 CR4/TM4 overflow Match between TM5 and TM5 CR5/TM5 overflow CSI0 transfer end I C transfer end CSI1 transfer end UART0 receive error UART0 receive end UART0 transfer end CSI2 transfer end UART1 receive error UART1 receive end UART1 transmit end CSI3 transfer end
2
0190H 01A0H 01B0H 01C0H 01D0H 01E0H 01F0H 0200H 0210H 0220H 0230H 0240H 0250H 0260H 0270H 0280H 0290H 02A0H 02B0H 02C0H 02D0H
00000190H 000001A0H 000001B0H 000001C0H 000001D0H 000001E0H 000001F0H 00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H 00000270H 00000280H 00000290H 000002A0H 000002B0H 000002C0H 000002D0H
CSI0 IC CSI1 UART0 UART0 UART0 CSI2 UART1 UART1 UART1 CSI3 CSI4 ADC DMA DMA DMA DMA RTC BRG
2
INTCSI1 INTSRE0 INTSR0 INTST0 INTCSI2 INTSRE1 INTSR1 INTST1 INTCSI3
INTCSI4Note 2 CSI4 transfer end INTAD INTDMA0 INTDMA1 INTDMA2 INTDMA3 INTROV INTBRG A/D conversion end DMA0 transfer end DMA1 transfer end DMA2 transfer end DMA3 transfer end RTC overflow BRG match
Note 1. Valid for the PD703201Y, 70F3201Y, 703204Y and 70F3204Y only. 2. Valid for the V850E/SA3 only. Remarks 1. Default Priority: Restored PC: Priority that applies when two or more maskable interrupt requests occur at the same time. The highest priority is 0. The value of the PC saved to EIPC or FEPC when interrupt servicing/exception processing is started. However, the value of the restored PC saved when an interrupt is acknowledged during division instruction (DIV, DIVH, DIVU, DIVHU) execution is the value of the PC of the current instruction (DIV, DIVH, DIVU, DIVHU). nextPC: The value of the PC to be processed after an interrupt/exception. 2. The execution address of the illegal instruction when an illegal op code exception occurs is calculated with (Restored PC - 4).
Preliminary Product Information U15436EJ1V0PM
33
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
7. CLOCK GENERATION FUNCTION
The clock generation function has the following features. Main clock oscillator * 2 to 17 MHz (@ VDD = 2.3 to 2.7 V operation) * 2 to 13.5 MHz (@ VDD = 2.2 to 2.7 V operation) Subclock oscillator * 32.768 kHz (@ VDD = 2.2 to 2.7 V operation) Internal system clock generation * 6 levels (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32) Peripheral clock generation Clock output function The following figure shows the configuration of the clock generation function.
FRC bit XT1 XT2 Subclock oscillator fXT fXT Prescaler 3 fX/26 to fX/29 RTC clock A/D converter IDLE mode CK2 to CK0 bits X1 X2 Main clock oscillator Main clock oscillator stop control STOP mode fX IDLE control fXX Prescaler 2 fXX/32 fXX/16 HALT mode
MFRC bit
Selector
fXX/8 fXX/4 fXX/2 fXX
HALT fCPU control fCLK
CPU clock Internal system clock
Prescaler 1
fXX to fXX/512
Peripheral clock
WDT clock control CLKOUT Port CM
fXW
WDT clock
Remark fX, fXX: Main clock frequency fXT: Subclock frequency fCPU: CPU clock frequency fCLK: Internal system clock frequency fXW: Watchdog timer clock frequency
34
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
8. POWER SAVE FUNCTION
The V850ES/SA2 and V850ES/SA3 have the following power save functions to realize an effective low-powerconsuming system. HALT mode: IDLE mode: STOP mode: Backup mode: Only the clock of the CPU is stopped in this mode. All operations on the chip other than oscillator operation are stopped in this mode. All operations on the chip other than subclock oscillator operation are stopped in this mode. The power supply other than for the subclock oscillator, real-time counter, and internal RAM can be disconnected. The following table shows the operating states of the on-chip peripheral functions in each mode.
Parameter VDD, EVDD, AVDD VDDBU CPU operation On-chip peripheral function operation Main clock oscillator operation Subclock oscillator operation Real-time counter function, RAM retention Release condition HALT Mode Power supplied Power supplied Stopped Enabled Stopped IDLE Mode STOP Mode Backup Mode Power OFF possible
Enabled Enabled Enabled * Non-maskable interrupt request * Unmasked maskable interrupt request * RESET pin input
Stopped
RESET pin input after power is supplied
Preliminary Product Information U15436EJ1V0PM
35
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
* Backup mode overview The V850ES/SA2 and V850ES/SA3 are put in backup mode by stopping supplying power other than the backup power supply (VDDBU) in STOP mode. The backup power supply supplies power only to the subclock oscillator, real-time counter, and internal RAM, as shown in the figure below. Other on-chip functions including the CPU cannot operate since the power supply is stopped.
Power supply for backup VDDBU VDD AVDD EVDD
Power supply for operation Connect to VSS in backup mode
Backup power supply status flag (BPSF) RAM Real-time counter Subclock oscillator
CPU ROM Peripheral function Main clock oscillator
A/D converter
I/O function
D/A converter
VSSBU
VSS
AVSS
EVSS
In backup mode, subclock oscillator operation, real-time counter count operation, and internal RAM data retention are enabled. If the voltage is lower than the data retention voltage in backup mode, a backup power supply status flag (BPSF) is set and that internal RAM retention data can be detected as invalid. When this flag is set, the real-time counter and the RAM should be initialized at reset start.
RESET (input) VDD, EVDD, AVDD VDDBU Backup power supply status flag (BPSF)
Normal STOP Reset operation mode mode
(VDDBU is lower than data retention voltage)
Backup mode
CPU status
Reset Oscillation mode stabilization
Normal operation
BPSF STOP clear execution
BPSF confirmed BPSF (set initialization) cleared
36
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
9. TIMER/COUNTER FUNCTION
The timer/counter function has the following features. 16-bit timer/counter (TM0, TM1) * Capture/compare common registers: 2 for each * Interrupt request sources * Capture/match interrupt requests: 2 sources for each * Overflow interrupt requests: 1 source for each * Timer/counter count clock sources: 2 types (Selection of external pulse input or internal system clock division) * Either free-running mode or overflow stop mode can be selected as the operation mode when the timer/counter overflows * Timer/counter can be cleared by a match of the timer/counter and a compare register * External pulse outputs: 1 for each 8-bit timers (TM2 to TM5) * Stand-alone mode (mode in which a single timer is used) * Interval timer * External event counter * Square-wave output * PWM output * Cascade connection mode (mode in which two timers are used connected in cascade: 16-bit resolution) * 16-bit resolution interval timer * 16-bit resolution external event counter * 16-bit resolution square-wave output
Preliminary Product Information U15436EJ1V0PM
37
3' < < ) )< ) )<
7KH IROORZLQJ ILJXUH VKRZV WKH FRQILJXUDWLRQ RI WKH WLPHUFRXQWHU IXQFWLRQ 70 70
Selector
fXX
fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256
Clear & start TMn (16 bits) TIn TCLRn TCLRn/TIn/INTPn0 INTPn1
Note 1
INTOVn
Note 3 Note 3 Note 3
Note 2 Note 2
CCn0 CCn1
S R
Note 4
Q Q
Selector
INTPn0
TOnNote 1
INTCCn0 INTCCn1
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I;; 0DLQ FORFN IUHTXHQF\
3UHOLPLQDU\ 3URGXFW ,QIRUPDWLRQ 8(-930
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2) TM2 to TM5
Internal bus
Mask circuit
8-bit compare register n (CRn) Match TIn Count clockNote
Selector
Selector
INTTMn
8-bit counter n OVF (TMn) Clear
Selector
S INV Q R
TOn
3 Selector
S R
Q
Invert level
TCLn2 TCLn1 TCLn0 Timer clock select register n (TCLn)
TCEn TMCn6 TMCn4 LVSn LVRn TMCn1 TOEn Timer mode control register n (TMCn) Internal bus
Note The count clock is set by the TCLn register. * When n = 2, 3 fXX/4 fXX/8 fXX/16 fXX/32 fXX/128 fXX/512 Remarks 1. " * When n = 4, 5 fXX/4 fXX/8 fXX/16 fXX/32 fXX/128 fXX/256 ]" is a signal that can be directly connected to a port.
2. n = 2 to 5
Preliminary Product Information U15436EJ1V0PM
39
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
10. REAL-TIME COUNTER FUNCTION
The real-time counter function has the following features. Includes counters of weeks, days, hours, minutes, and seconds, and can count up to 4,095 weeks. Counters of weeks, days, hours, minutes, and seconds can be read during operation and while operation is stopped. Week counter overflow interrupt request occurrence (INTROV) Interval interrupt request occurrence (INTRTC) at a fixed interval (can be selected from the following) 0.015625 seconds, 0.03125 seconds, 0.0625 seconds, 0.125 seconds, 0.25 seconds, 0.5 seconds, 1 second, 1 minute, 1 hour, 1 day When subclock (fXT) is selected, operable only with power supply to VDDBU. The following figure shows the configuration of the real-time counter function.
0.015625 seconds/0.03125 seconds/0.0625 seconds/0.125 seconds/ 0.25 seconds/0.5 seconds
Selector
INTRTC
Count clock = 32.768 kHz fXT fX/2 to fX/29
6
1 second
1 minute
1 hour
1 day
Selector
Subcounter (15 bits)
Second counter (6 bits)
Minute counter (6 bits)
Hour counter (5 bits)
Day counter (3 bits)
Week counter (12 bits)
INTROV
Count enable/ disable circuit Second counter write buffer Minute counter write buffer Hour counter write buffer Day counter write buffer Week counter write buffer
Internal bus
Remark fX:
Main clock frequency
fXT: Subclock frequency
40
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
11. WATCHDOG TIMER FUNCTION
The watchdog timer has the following functions. Watchdog timer Interval timer Timer for oscillation stabilization The following figure shows the configuration of the watchdog timer function.
OSCMD RUN Clear fXW 13-bit divider fXW/213 fXW/212 fXW/211 fXW/210 fXW/29 fXW/28 fXW/27 fXW/26 fXW/25
Selector
Clear 8-bit counter
INTWDTM OVF Output control INTWDT WDTRES OSTOVF WDTM3, WDTM4
OSTS0 to OSTS2, WDCS0 to WDCS2
Remarks 1. WDTRES: OSTOVF: OSCMD: fXW:
Reset signal triggered by WDT overflow Overflow signal for oscillation stabilization Timer mode signal for oscillation stabilization Watchdog timer clock frequency fXW = fXX/2
2. During counting of oscillation stabilization time: fXW = fX/2 Other than above:
Preliminary Product Information U15436EJ1V0PM
41
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
12. SERIAL INTERFACE FUNCTION
The V850ES/SA2 and V850ES/SA3 include the following three types of serial interfaces.
Type 3-wire serial I/O Asynchronous serial interface I2C busNote V850ES/SA2 4 channels (CSI0 to CSI3) 2 channels (UART0, UART1) 1 channel (I2C)Note V850ES/SA3 5 channels (CSI0 to CSI4)
Note Available only in the PD703201Y, 703204Y, 70F3201Y, and 70F3204Y. Some functions are used alternately as follows. * CSI0/I C
2
* CSI1/UART0 * CSI2 * UART1 * CSI3 * CSI4 (V850ES/SA3 only)
12.1 3-Wire Serial I/O (CSIn)
Remark In this section, the value of n is as follows. n = 0 to 3 (V850ES/SA2) n = 0 to 4 (V850ES/SA3) The 3-wire serial I/O (CSIn) transfers data using following three lines. * SCKn (serial clock) * SOn (serial data output) * SIn (serial data input) The 3-wire serial I/O (CSIn) has the following features. Transfer data length: Fixed to 8 bits Transfer data MSB/LSB first can be switched Transfer clock can be selected from eight clocks (seven master clocks, one slave clock) Transmit/receive mode or receive-only mode can be specified On-chip 8-bit transmit buffer Transfer data transmit/receive timing with respect to the transfer clock can be changed
42
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
The following figure shows the configuration of the 3-wire serial I/O (CSIn).
CKSn0 to CKSn2 fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 TOFm SCKn Transfer mode controller CSIEn, TRMDn, DIRn, CKPn, DAPn
Selector
INTCSIn Transfer clock controller CSOTn
Transfer data controller
Transmit buffer (SOTBn)
Selector
SOn
SIn
SOn latch Shift register (SIOn)
Remarks 1. When n = 0: m = 2 When n = 1: m = 3 When n = 2: m = 4 When n = 3: m = 5 When n = 4: m = 5 (V850ES/SA3 only) 2. fXX: Main clock frequency
Preliminary Product Information U15436EJ1V0PM
43
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
12.2 Asynchronous Serial Interface (UART0 and UART1)
The asynchronous serial interface (UART0 and UART1) has the following features. Two modes * Operation stop mode (used when serial transfers are not performed to enable a reduction in power consumption) * Asynchronous serial interface mode Full-duplex transmission 2-pin configuration * TXD0 and TXD1: Transmit data output pins * RXD0 and RXD1: Receive data input pins 3 types of interrupt sources * Receive error interrupt (INTSRE0 and INTSRE1) * Receive end interrupt (INTSR0 and INTSR1) * Transmit end interrupt (INTST0 and INTST1) Character length: 7 bits/8 bits Parity function: Odd, even, 0, none Transmission stop bit: 1 bit/2 bits On-chip baud rate generator The following figure shows the configuration of the asynchronous serial interface (UART0 and UART1).
Internal bus
Asynchronous serial interface mode register n (ASIMn)
Receive buffer (RXBn)
Transmit buffer (TXBn)
RXDn TXDn
Receive shift register
Transmit shift register
Reception control parity check Parity Framing Overrun
Addition of transmission control parity
INTSTn INTSRn
INTSREn BRGn
Remark n = 0, 1
44
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
12.3 I C Bus (I C) (PD703201Y, 703204Y, 70F3201Y, 70F3204Y)
2 2
The I C bus has the following features. Two modes * Operation stop mode (used when serial transfers are not performed to enable a reduction in power consumption) * I C bus mode (supporting multi masters)
2
2
The following figure shows the configuration of the I C bus
2
Internal bus IIC status register 0 (IICS)
MSTS ALD EXC COI TRC ACKD STD SPD
IIC control register (IICC) SDA Noise eliminator Slave address register (SVA) Match signal
IICE LREL WREL SPIE WTIM ACKE STT SPT
CLEAR SET SO latch DQ CL1, CL0
IIC shift register (IIC)
N-ch open drain output
Data hold time correction circuit
ACK detector
Wake up controller ACK detector
Start condition detector
SCL Noise eliminator
Stop condition detector Interrupt request signal generator
Serial clock counter
INTIIC
Serial clock controller N-ch open drain output fxx TM4 output Prescaler
Serial clock wait controller
CLD
DAD
SMC
DFC
CL1
CL0
CLX
IIC clock select register (IICCL) Internal bus
IIC function expansion register (IICX)
Remark fXX: Main clock frequency
Preliminary Product Information U15436EJ1V0PM
45
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
13. A/D CONVERTER
The A/D converter has the following features. 10-bit resolution 12 channels (V850ES/SA2) 16 channels (V850ES/SA3) Successive comparison approximation method Power fail detection function available Operation voltage: AVDD = AVREF0 = 2.2 to 2.7 V Analog input voltage: AVSS to AVREF0 Conversion rate: 9.5 to 1.50 s The following figure shows the configuration of the A/D converter.
ADS0 to ADS3 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12Note ANI13Note ANI14Note ANI15Note
Controller
INTAD
Analog input side C array
Selector
Reference side C array Comparator
Successive approximation register (SAR)
A/D conversion result register (ADCR) AVREF0 AVDD AVSS
Note V850ES/SA3 only
46
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
The following figure shows the configuration of the power fail detection function.
ADS0 to ADS3 PFCM ANI0 ANI1 ANI2 ANI3 PFEN
Selector
ANI4 ANI5
INTAD
ANI8 ANI9 ANI10 ANI11 ANI12Note ANI13Note ANI14Note ANI15Note
Selector
ANI6 ANI7
A/D converter
Comparator
Power-fail comparison threshold value register (PFT)
Note V850ES/SA3 only
Preliminary Product Information U15436EJ1V0PM
47
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
14. D/A CONVERTER
The D/A converter has the following features. 8-bit resolution x 2 channels (DAC0, DAC1) R string method Conversion time: 20 s max. (AVREF1 = 2.2 to 2.7 V) Analog output voltage: AVREF1 x m/256 (m = 0 to 255; Value set in the DACSn register) Operation mode: Normal mode/real-time output mode Remark n = 0, 1 The following figure shows the configuration of the D/A converter.
DACS0 DACS0 write DAMD0 INTTM2 AVREF1 R string resistor AVSS ANO0 DACE0
DACS1 DACS1 write DAMD1 INTTM3 DACE1
R string resistor
ANO1
48
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
15. DMA FUNCTION
The DMA function has the following features. Transfer unit: 8 bits/16 bits Maximum transfer count: 65,536 (2 ) times Transfer type: 2-cycle transfer Transfer mode: Single transfer Transfer request: Request via interrupt from on-chip peripheral I/O or external pins, request via software trigger Transfer object: On-chip peripheral I/O, internal RAM, external memory The relationship between the transfer type and transfer object is shown below (: Transfer enabled, x: Transfer disabled).
Transfer Destination Transfer Source On-chip peripheral I/O Internal RAM External memory x On-Chip Peripheral I/O Internal RAM External Memory
16
The following figure shows the configuration of the DMA function.
V850ES core On-chip peripheral I/O On-chip peripheral I/O bus
CPU BCU
IRIF
Internal RAM
Data control block
Address control block
DSAnH/ DSAnL DDAnH/ DDAnL
INTDMAn DMARQn DMACTVn External bus
Count control block Channel control block
DBCn DCHCn DADCn DMAC
External I/O
External RAM
External ROM
Remark n = 0 to 3
Preliminary Product Information U15436EJ1V0PM
49
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
16. ROM CORRECTION FUNCTION
The ROM correction function is a function that replaces part of a program in the mask ROM with a program in the internal RAM for execution. First, the address where the program replacement should start (correction address) is set in the correction address register (CORADn). When the CPU reads the instruction of the address set in CORADn, the instruction is replaced with the DBTRAP instruction and the program jumps to 00000060H. A value that is the address saved in the DBPC minus 2 (address to which ROM correction generated) is compared with the address set in CORADn, and the program jumps to the correction program on the corresponding RAM. After executing the correction program, a restore address is set in the DBPC, the DBRET instruction is executed, and then execution is restored to the normal program. Up to four correction addresses can be specified in CORADn. Remark n = 3 The following figure shows the configuration of ROM correction.
Instruction address bus
Correction address register (CORADn)
Comparator
DBTRAP instruction generation block
ROM (1 MB space)
Correction control register (CORENn bit)
Instruction replacement block
Instruction data bus
Remark n = 0 to 3
50
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
17. RESET FUNCTION
When a low-level signal is input to the RESET pin or the watchdog timer overflows (WDTRES), a system reset is applied and the various on-chip hardware devices are reset to their initial states. When the RESET pin goes from low level to high level, or when the WDTRES signal is automatically canceled, the reset state is released. When reset is released via RESET pin input, the CPU starts execution of the program after securing the oscillation stabilization time (OSTS register reset value: 2 /fXX). When reset is released by the WDTRES signal, the main clock oscillator does not stop and oscillation stabilization time is not inserted. The following figure shows the configuration of the reset function.
19
RESET
Reset controller
Reset signal
Count clock
Watchdog timer Stop
Overflow
Interrupt function
Preliminary Product Information U15436EJ1V0PM
51
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
18. FLASH MEMORY (PD70F3201, 70F3201Y, 70F3204, 70F3204Y)
The PD70F3201 and 70F3201Y, and 70F3204 and 70F3204Y are the flash memory versions of the V850ES/SA2 and V850ES/SA3, respectively, and incorporate 256 KB of flash memory. Writing to flash memory can be performed while the device is mounted on the target system (on board). Writing is performed using a dedicated flash programmer connected to the target system or to a writing adapter. The flash memory has the following features. Flash memory: 256 KB (4 KB x 4 blocks, 60 KB x 4 blocks) Erasure/writing possible using single power supply (VDD = 2.2 to 2.7 V) Erasure unit * Overall area batch erasure (256 KB) * Block units erasure (4 KB/block, 60 KB/block) Erasure/writing method * Serial mode (using CSI0 or UART0) * Self-programming mode
52
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
An overview of flash memory programming is shown below. Pins used in programming * Power supply pins (VDD, EVDD, AVDD, VSS, EVSS, AVSS, VDDBU, VSSBU) * Mode pins (FLMD0, FLMD1) * Clock supply pins (X1, X2) * Serial communication pins (SCK0, SO0, SI0 or RXD0, TXD0) * RESET pin Programming timing The following figure shows the programming timing (overview) when using UART.
VDD VDD 0V VDD RESET (input) 0V VDD FLMD1 (input) 0V VDD FLMD0 (input) 0V VDD RXD0 (input) 0V VDD TXD0 (output) 0V Oscillation stabilization Power ON Reset release Communication mode selection Flash control command communication (erasure, writing, etc.) (UART mode only)
Preliminary Product Information U15436EJ1V0PM
53
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
19. INSTRUCTION SET LIST 19.1 Conventions
(1) Register symbols used to describe operands
Register Symbol reg1 reg2 General-purpose register: General-purpose register: Explanation Used as source register. Used mainly as destination register. Also used as source register in some instructions. Used mainly to store the remainder of division results and the higher 32 bits of multiplication results.
reg3
General-purpose register:
bit#3 immX dispX regID vector cccc sp ep listX
3-bit data for specifying the bit number X bit immediate data X bit displacement data System register number 5-bit data that specifies the trap vector (00H to 1FH) 4-bit data that shows the condition code Stack pointer (r3) Element pointer (r30) X item register list
(2) Register symbols used to describe opcodes
Register Symbol R r w d I i cccc CCCC bbb L S Explanation 1-bit data of the code that specifies reg1 or regID 1-bit data of the code that specifies reg2 1-bit data of the code that specifies reg3 1-bit displacement data 1-bit immediate data (indicates the higher bits of immediate data) 1-bit immediate data 4-bit data that shows the condition codes 4-bit data that shows the condition codes of the Bcond instruction 3-bit data for specifying the bit number 1-bit data that specifies a program register in the register list 1-bit data that specifies a system register in the register list
54
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(3) Register symbols used in operation
Register Symbol GR [ ] SR [ ] zero-extend (n) sign-extend (n) load-memory (a, b) store-memory (a, b, c) load-memory-bit (a, b) store-memory-bit (a, b, c) saturated (n) Input for General-purpose register System register Expand n with zeros until word length. Expand n with signs until word length. Read size b data from address a. Write data b into address a in size c. Read bit b of address a. Write c to bit b of address a. Execute saturated processing of n (n is a 2's complement). If, as a result of calculations, n 7FFFFFFFH, let it be 7FFFFFFFH. n 80000000H, let it be 80000000H. Reflects the results in a flag. Byte (8 bits) Halfword (16 bits) Word (32 bits) Addition Subtraction Bit concatenation Multiplication Division Remainder from division results Logical product Logical sum Exclusive OR Logical negation Logical shift left Logical shift right Arithmetic shift right Explanation
result Byte Half-word Word + - ll x / % AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by
(4) Register symbols used in an execution clock
Register Symbol i r l Explanation If executing another instruction immediately after executing the first instruction (issue). If repeating execution of the same instruction immediately after executing the first instruction (repeat). If using the results of instruction execution in the instruction immediately after the execution (latency).
Preliminary Product Information U15436EJ1V0PM
55
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(5) Register symbols used in flag operations
Identifier (Blank) 0 X R No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. Explanation
(6) Condition codes
Condition Name (cond) V NV C/L Condition Code (cccc) 0000 1000 0001 Condition Expression Explanation
OV = 1 OV = 0 CY = 1
Overflow No overflow Carry Lower (less than) No carry Not lower (greater than or equal) Zero Equal Not zero Not equal Not higher (less than or equal) Higher (greater than) Negative Positive -- Always (unconditional) Saturated Less than signed Greater than or equal signed Less than or equal signed Greater than signed
NC/NL
1001
CY = 0
Z/E
0010
Z=1
NZ/NE
1010
Z=0
NH H N P T SA LT GE LE GT
0011 1011 0100 1100 0101 1101 0110 1110 0111 1111
(CY or Z) = 1 (CY or Z) = 0 S=1 S=0
SAT = 1 (S xor OV) = 1 (S xor OV) = 0 ((S xor OV) or Z) = 1 ((S xor OV) or Z) = 0
56
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
19.2 Instruction Set (In Alphabetical Order)
(1/6)
Mnemonic Operand Opcode Operation Execution Clock i ADD reg1,reg2 imm5,reg2 ADDI imm16,reg1,reg2 rrrrr001110RRRRR rrrrr010010iiiii rrrrr110000RRRRR iiiiiiiiiiiiiiii AND ANDI reg1,reg2 imm16,reg1,reg2 rrrrr001010RRRRR rrrrr110110RRRRR iiiiiiiiiiiiiiii Bcond disp9 ddddd1011dddc ccc if conditions are satisfied When conditions are satisfied When conditions are not satisfied BSH reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll 1 1 1 x 0 x x 2 2 2 GR[reg2]GR[reg2]AND GR[reg1] GR[reg2]GR[reg1]AND zero-extend(imm16) 1 1 1 1 1 1 0 0 x 0 x x GR[reg2]GR[reg2]+GR[reg1] GR[reg2]GR[reg2]+sign-extend(imm5) GR[reg2]GR[reg1]+sign-extend(imm16) 1 1 1 r 1 1 1 l 1 1 1 CY OV S x x x x x x x x x Z SAT x x x Flags
Note 1 then PCPC+sign-extend(disp9)
Note 2 Note 2 Note 2
1
1
1
wwwww01101000010 GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) BSW reg2,reg3 rrrrr11111100000 GR[reg3]GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR 1 1 1 x 0 x x
wwwww01101000000 [reg2] (23 : 16) ll GR[reg2] (31 : 24) CALLT imm6 0000001000iiiiii CTPCPC+2(return PC) CTPSWPSW adrCTBP+zero-extend(imm6 logically shift left by 1) PCCTBP+zero-extend(Load-memory(adr,Half-word)) CLR1 bit#3, disp16[reg1] 10bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd 3 3 3 x 4 4 4
Z flagNot(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,0)
Note 3 Note 3 Note 3
reg2,[reg1]
rrrrr111111RRRRR 0000000011100100
adrGR[reg1]
3
3
3
x
Z flagNot(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,0)
Note 3 Note 3 Note 3
CMOV
cccc,imm5,reg2,reg3
rrrrr111111iiiii wwwww011000cccc0
if conditions are satisfied then GR[reg3]sign-extended(imm5) else GR[reg3]GR[reg2]
1
1
1
cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R R R R
if conditions are satisfied else GR[reg3]GR[reg2]
1
1
1
wwwww011001cccc0 then GR[reg3]GR[reg1]
CMP
reg1,reg2 imm5,reg2
rrrrr001111RRRRR rrrrr010011iiiii 0000011111100000 0000000101000100
resultGR[reg2]-GR[reg1] resultGR[reg2]-sign-extend(imm5) PCCTPC PSWCTPSW PCDBPC PSWDBPSW
1 1 3
1 1 3
1 1 3
x x R
x x R
x x R
x x R R
CTRET
DBRET
0000011111100000 0000000101000110
3
3
3
R
R
R
R
R
Preliminary Product Information U15436EJ1V0PM
57
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2/6)
Mnemonic Operand Opcode Operation Execution Clock i DBTRAP 1111100001000000 DBPCPC+2 (restored PC) DBPSWPSW PSW.NP1 PSW.EP1 PSW.ID1 PC00000060H DI 0000011111100000 0000000101100000 DISPOSE imm5,list12 0000011001iiiiiL LLLLLLLLLLL00000 spsp+zero-extend(imm5 logically shift left by 2) GR[reg in list12]Load-memory(sp,Word) spsp+4 repeat 2 steps above until all regs in list12 is loaded imm5,list12,[reg1] 0000011001iiiiiL spsp+zero-extend(imm5 logically shift left by 2) n+3 n+3 n+3
Note 4 Note 4 Note 4
Flags
r 3
l 3
CY OV S
Z SAT
3
PSW.ID1
1
1
1
n+1 n+1 n+1
Note 4 Note 4 Note 4
LLLLLLLLLLLRRRRR R[reg in list12]Load-memory(sp,Word) Note 5 spsp+4 repeat 2 steps above until all regs in list12 is loaded PCGR[reg1] DIV reg1,reg2,reg3 rrrrr111111RRRRR GR[reg2]GR[reg2}/GR[reg1]
35 35 35
wwwww01011000000 GR[reg3]GR[reg2]%GR[reg1] DIVH reg1,reg2 reg1,reg2,reg3 rrrrr000010RRRRR rrrrr111111RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 GR[reg2]GR[reg2]/GR[reg1]
Note 6
35 35 35 35 35 35
x x
x x
x x
wwwww01010000000 GR[reg3]GR[reg2]%GR[reg1] DIVHU reg1,reg2,reg3 rrrrr111111RRRRR GR[reg2]GR[reg2]/GR[reg1]Note 6 34 34 34 x x x
wwwww01010000010 GR[reg3]GR[reg2]%GR[reg1] DIVU reg1,reg2,reg3 rrrrr111111RRRRR GR[reg2]GR[reg2]/GR[reg1] 34 34 34 x x x
wwwww01011000010 GR[reg3]GR[reg2]%GR[reg1] EI 1000011111100000 0000000101100000 HALT 0000011111100000 0000000100100000 HSW reg2,reg3 rrrrr11111100000 wwwww01101000100 JARL disp22,reg2 rrrrr11110dddddd ddddddddddddddd0 Note 7 JMP JR [reg1] disp22 00000000011RRRRR 0000011110dddddd ddddddddddddddd0 Note 7 LD.B disp16[reg1],reg2 rrrrr111000RRRRR dddddddddddddddd LD.BU disp16[reg1],reg2 rrrrr11110bRRRRR dddddddddddddd1 Notes 8, 10 adrGR[reg1]+sign-extend(disp16) GR[reg2]sign-extend(Load-memory(adr,Byte)) adrGR[reg1]+sign-extend(disp16) GR[reg2]zero-extend(Load-memory(adr,Byte)) 1 1 1 1
Note 11 Note 11
PSW.ID0
1
1
1
Stop
1
1
1
GR[reg3]GR[reg2](15 : 0) ll GR[reg2] (31 : 16)
1
1
1
x
0
x
x
GR[reg2]PC+4 PCPC+sign-extend(disp22)
2
2
2
PCGR[reg1] PCPC+sign-extend(disp22)
3 2
3 2
3 2
58
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(3/6)
Mnemonic Operand Opcode Operation Execution Clock i LD.H disp16[reg1],reg2 rrrrr111001RRRRR ddddddddddddddd0 adrGR[reg1]+sign-extend(disp16) GR[reg2]sign-extend(Load-memory(adr,Half1 r 1 l
Note 11
Flags
CY OV S
Z SAT
Note 8 word)) LDSR reg2,regID rrrrr111111RRRRR 0000000000100000 Note 12 LD.HU disp16[reg1],reg2 rrrrr111111RRRRR ddddddddddddddd1 Note 8 LD.W disp16[reg1],reg2 rrrrr111001RRRRR ddddddddddddddd1 Note 8 MOV reg1,reg2 imm5,reg2 imm32,reg1 rrrrr000000RRRRR rrrrr010000iiiii GR[reg2]GR[reg1] GR[reg2]sign-extend(imm5) 1 1 2 1 1 2 1 1 2 adrGR[reg1]+sign-exend(disp16) GR[reg2]Load-memory(adr,Word) 1 1
Note 11
SR[regID]GR[reg2]
Other than regID = PSW regID = PSW
1 1
1 1
1 1 x x x x x
adrGR[reg1]+sign-exend(disp16) GR[reg2]zero-extend(Load-memory(adr,half-word)
1
1
Note 11
00000110001RRRRR GR[reg1]imm32 iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii
MOVEA
imm16,reg1,reg2
rrrrr110001RRRRR iiiiiiiiiiiiiiii
GR[reg2]GR[reg1]+sign-extend(imm16)
1
1
1
MOVHI
imm16,reg1,reg2
rrrrr110010RRRRR iiiiiiiiiiiiiiii
GR[reg2]GR[reg1]+(imm16 ll 0 )
16
1
1
1
MUL
reg1,reg2,reg3
rrrrr111111RRRRR wwwww01000100000
GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1]
1
4
5
imm9,reg2,reg3
rrrrr111111iiiii wwwww01001IIII00 Note 13
GR[reg3] ll GR[reg2]GR[reg2]xsign-extend(imm9)
1
4
5
MULH
reg1,reg2 imm5,reg2
rrrrr000111RRRRR rrrrr010111iiiii rrrrr110111RRRRR iiiiiiiiiiiiiiii
GR[reg2]GR[reg2]Note 6xGR[reg1]Note 6 GR[reg2]GR[reg2] GR[reg2]GR[reg1]
Note 6
1 1 1
1 1 1
2 2 2
xsign-extend(imm5) ximm16
MULHI
imm16,reg1,reg2
Note 6
MULU
reg1,reg2,reg3
rrrrr111111RRRRR wwwww01000100010
GR[reg3] ll GR[reg2]GR[reg2]xGR[reg1]
1
4
5
imm9,reg2,reg3
rrrrr111111iiiii wwwww01001IIII10 Note 13
GR[reg3] ll GR[reg2]GR[reg2]xzero-extend(imm9)
1
4
5
NOP NOT NOT1 reg1,reg2 bit#3,disp16[reg1]
0000000000000000 Pass at least one clock cycle doing nothing. rrrrr000001RRRRR GR[reg2]NOT(GR[reg1])
1 1 3
1 1 3
1 1 3 0 x x x
01bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot(Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,Z flag)
Note 3 Note 3 Note 3
reg2,[reg1]
rrrrr111111RRRRR 0000000011100010
adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,Z flag)
3
3
3
x
Note 3 Note 3 Note 3
Preliminary Product Information U15436EJ1V0PM
59
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(4/6)
Mnemonic Operand Opcode Operation Execution Clock i OR ORI reg1,reg2 imm16,reg1,reg2 rrrrr001000RRRRR rrrrr110100RRRRR iiiiiiiiiiiiiiii PREPARE list12,imm5 0000011110iiiiiL Store-memory(sp-4,GR[reg in list12],Word) repeat 1 step above until all regs in list12 is stored spsp-zero-extend(imm5) list12,imm5, sp/imm
Note 14
Flags
r 1 1
l 1 1
CY OV S 0 0 x x
Z SAT x x
GR[reg2]GR[reg2]OR GR[reg1] GR[reg2]GR[reg1]OR zero-extend(imm16)
1 1
n+1 n+1 n+1
Note 4 Note 4 Note 4
LLLLLLLLLLL00001 spsp-4
0000011110iiiiiL LLLLLLLLLLLff011 imm16/imm32
Store-memory(sp-4,GR[reg in list12],Word) spsp-4 repeat 1 step above until all regs in list12 is stored
n+2 n+2 n+2
Note 4 Note 4 Note 4 Note16 Note16 Note16
Note 15 spsp-zero-extend(imm5) epsp/imm RETI 0000011111100000 if PSW.EP=1 0000000101000000 then PC EIPC PSW EIPSW else if PSW.NP=1 then else PC PC FEPC EIPC PSW FEPSW PSW EIPSW SAR reg1,reg2 rrrrr111111RRRRR 0000000010100000 imm5,reg2 rrrrr010101iiiii GR[reg2]GR[reg2]arithmetically shift right by GR[reg1] GR[reg2]GR[reg2]arithmetically shift right by zero-extend (imm5) SASF cccc,reg2 rrrrr1111110cccc 0000001000000000 if conditions are satisfied then GR[reg2](GR[reg2]Logically shift left by 1) OR 00000001H else GR[reg2](GR[reg2]Logically shift left by 1) OR 00000000H SATADD reg1,reg2 imm5,reg2 SATSUB SATSUBI reg1,reg2 imm16,reg1,reg2 rrrrr000110RRRRR rrrrr010001iiiii rrrrr000101RRRRR rrrrr110011RRRRR iiiiiiiiiiiiiiii SATSUBR reg1,reg2 SETF cccc,reg2 rrrrr000100RRRRR rrrrr1111110cccc 0000000000000000 GR[reg2]saturated(GR[reg1]-GR[reg2]) If conditions are satisfied then GR[reg2]00000001H else GR[reg2]00000000H SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit(adr,bit#3)) Store-memory-bit(adr,bit#3,1) reg2,[reg1] rrrrr111111RRRRR 0000000011100000 adrGR[reg1] Z flagNot(Load-memory-bit(adr,reg2)) Store-memory-bit(adr,reg2,1) GR[reg2]saturated(GR[reg2]+GR[reg1]) GR[reg2]saturated(GR[reg2]+sign-extend(imm5) GR[reg2]saturated(GR[reg2]-GR[reg1]) GR[reg2]saturated(GR[reg1]-sign-extend(imm16)
3
3
3
R
R
R
R
R
1
1
1
x
0
x
x
1
1
1
x
0
x
x
1
1
1
1 1 1 1
1 1 1 1
1 1 1 1
x x x x
x x x x
x x x x
x x x x
x x x x
1 1
1 1
1 1
x
x
x
x
x
3
3
3
x
Note 3 Note 3 Note 3
3
3
3
x
Note 3 Note 3 Note 3
60
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(5/6)
Mnemonic Operand Opcode Operation Execution Clock i SHL reg1,reg2 rrrrr111111RRRRR 0000000011000000 imm5,reg2 rrrrr010110iiiii GR[reg2]GR[reg2] logically shift left by zero-extend(imm5) SHR reg1,reg2 rrrrr111111RRRRR 0000000010000000 imm5,reg2 rrrrr010100iiiii GR[reg2]GR[reg2] logically shift right by zero-extend(imm5) SLD.B disp7[ep],reg2 rrrrr0110ddddddd adrep+zero-extend(disp7) GR[reg2]sign-extend(Load-memory(adr,Byte)) SLD.BU disp4[ep],reg2 rrrrr0000110dddd adrep+zero-extend(disp4) 1 1
Note 9
Flags
r 1
l 1
CY OV S x 0 x
Z SAT x
GR[reg2]GR[reg2] logically shift left by GR[reg1]
1
1
1
1
x x
0
x x
x x
GR[reg2]GR[reg2] logically shift right by GR[reg1]
1
1
1
0
1
1
1
x
0
x
x
1
1
Note 9
Note 17 GR[reg2]zero-extend(Load-memory(adr,Byte)) SLD.H disp8[ep],reg2 rrrrr1000ddddddd adrep+zero-extend(disp8) word)) SLD.HU disp5[ep],reg2 r r r r r 0 0 0 0 1 1 1 d d d d adrep+zero-extend(disp5) Notes 17, 19 GR[reg2]zero-extend(Load-memory(adr,Halfword)) SLD.W disp8[ep],reg2 rrrrr1010dddddd0 adrep+zero-extend(disp8) 1 1
Note 9
1
1
Note 9
Note 18 GR[reg2]sign-extend(Load-memory(adr,Half-
1
1
Note 9
Note 20 GR[reg2]Load-memory(adr,Word) SST.B reg2,disp7[ep] rrrrr0111ddddddd adrep+zero-extend(disp7) Store-memory(adr,GR[reg2],Byte) SST.H reg2,disp8[ep] rrrrr1001ddddddd adrep+zero-extend(disp8) 1 1 1 1 1 1
Note 18 Store-memory(adr,GR[reg2],Half-word) SST.W reg2,disp8[ep] rrrrr1010dddddd1 adrep+zero-extend(disp8) 1 1 1
Note 20 Store-memory(adr,GR[reg2],Word) ST.B reg2,disp16[reg1] rrrrr111010RRRRR dddddddddddddddd ST.H reg2,disp16[reg1] rrrrr111011RRRRR ddddddddddddddd0 Note 8 ST.W reg2,disp16[reg1] rrrrr111011RRRRR ddddddddddddddd1 Note 8 STSR regID,reg2 rrrrr111111RRRRR 0000000001000000 SUB SUBR SWITCH reg1,reg2 reg1,reg2 reg1 rrrrr001101RRRRR rrrrr001100RRRRR GR[reg2]GR[reg2]-GR[reg1] GR[reg2]GR[reg1]-GR[reg2] 1 1 5 1 1 5 1 1 5 x x x x x x x x GR[reg2]SR[regID] 1 1 1 adrGR[reg1]+sign-extend(disp16) Store-memory (adr,GR[reg2], Word) 1 1 1 adrGR[reg1]+sign-extend(disp16) Store-memory(adr,GR[reg2],Byte) adrGR[reg1]+sign-extend(disp16) Store-memory (adr,GR[reg2], Half-word) 1 1 1 1 1 1
00000000010RRRRR adr(PC+2) + (GR [reg1] logically shift left by 1) PC(PC+2) + (sign-extend (Load-memory (adr,Half-word))) logically shift left by 1
Preliminary Product Information U15436EJ1V0PM
61
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(6/6)
Mnemonic Operand Opcode Operation Execution Clock i SXB reg1 00000000101RRRRR GR[reg1]sign-extend (GR[reg1] (7 : 0)) SXH reg1 00000000111RRRRR GR[reg1]sign-extend (GR[reg1] (15 : 0)) TRAP vector 00000111111iiiii 0000000100000000 EIPC EIPSW PSW.EP PSW.ID PC PC+4 (Restored PC) PSW 1 1 00000040H (when vector is 00H to 3 3 3 1 1 1 1 r 1 l 1 CY OV S Z SAT Flags
ECR.EICC Interrupt Code
0FH)
00000050H (when vector is 10H to
1FH)
TST TST1 reg1,reg2 bit#3,disp16[reg1] rrrrr001011RRRRR resultGR[reg2] AND GR[reg1] 1 3 1 3 1 3 0 x x x
11bbb111110RRRRR adrGR[reg1]+sign-extend(disp16) dddddddddddddddd Z flagNot (Load-memory-bit (adr,bit#3)) adrGR[reg1] Z flagNot (Load-memory-bit (adr,reg2)) GR[reg2]GR[reg2] XOR GR[reg1] GR[reg2]GR[reg1] XOR zero-extend (imm16)
Note 3 Note 3 Note 3
reg2, [reg1]
rrrrr111111RRRRR 0000000011100110
3
3
3
x
Note 3 Note 3 Note 3
XOR XORI
reg1,reg2 imm16,reg1,reg2
rrrrr001001RRRRR rrrrr110101RRRRR iiiiiiiiiiiiiiii
1 1
1 1
1 1
0 0
x x
x x
ZXB ZXH
reg1 reg1
00000000100RRRRR 00000000110RRRRR
GR[reg1]zero-extend (GR[reg1] (7 : 0)) GR[reg1]zero-extend (GR[reg1] (15 : 0))
1 1
1 1
1 1
Notes 1. 2. 3. 4. 5. 6. 7. 8. 9.
dddddddd: Higher 8 bits of disp9. 3 clocks if the final instruction includes the PSW write access. If there is no wait state (3 + the number of read access wait states). n is the total number of list X load registers. (According to the number of wait states. Also, if there are no wait states, n is the number of list X registers.) RRRRR: Other than 00000. The lower halfword data only is valid. ddddddddddddddddddddd: The higher 21 bits of disp22. ddddddddddddddd: The higher 15 bits of disp16. According to the number of wait states (1 if there are no wait states).
10. b: Bit 0 of disp16. 11. According to the number of wait states (2 if there are no wait states). 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. rrrrr = regID specification RRRRR = reg2 specification 13. i i i i i : Lower 5 bits of imm9. I I I I : Lower 4 bits of imm9. 14. sp/imm: Specified by bits 19 and 20 of the sub-opcode.
62
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Notes 15. ff = 00: Load sp in ep. 01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep. 10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 16. If imm = imm32, n + 3 clocks. 17. r r r r r : Other than 00000. 18. ddddddd: Higher 7 bits of disp8. 19. dddd: Higher 4 bits of disp5. 20. dddddd: Higher 6 bits of disp8.
Preliminary Product Information U15436EJ1V0PM
63
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
20. ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Supply voltage Symbol VDD AVDD EVDD VDDBU AVSS EVSS VSSBU Input voltage Clock input voltage VI VK VKT Analog input voltage Analog reference voltage Output current, low VIAN AVREF IOL Other than X1, XT1, and port 7 X1, VDD = 2.2 to 2.7 V XT1, VDDBU = 2.2 to 2.7 V Port 7 AVREF0, AVREF1 Per pin Total for all pins Output current, high IOH Per pin Total for all pins Output voltage Operating ambient temperature Storage temperature VO TA VDD = 2.5 V 0.2 V Normal operation mode Flash programming mode Tstg Conditions Ratings -0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6 -0.5 to +0.5 -0.5 to +0.5 -0.5 to +0.5 -0.5 to EVDD + 0.3Note -0.5 to VDD + 0.3
Note
Unit V V V V V V V V V V V V mA mA mA mA V C C C C
-0.5 to VDDBU + 0.3 -0.5 to AVDD + 0.3 -0.5 to AVDD + 0.3 4 100 -4 -100
Note
Note
Note
-0.5 to VDD + 0.3 V -40 to +85 T.B.D. -65 to +150 T.B.D.
PD703201, 703201Y, 703204, 703204Y PD70F3201, 70F3201Y, 70F3204, 70F3204Y
Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage. Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open-drain pins or open-collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation.
64
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Capacitance (TA = 25C, VDD = AVDD = EVDD = VDDBU = VSS = AVSS = EVSS = VSSBU = 0 V)
Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO Conditions fX = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 10 10 10 Unit pF pF pF
Operating Conditions (VDD = AVDD = EVDD = VDDBU)
Parameter Internal system clock frequency Symbol fCLK Conditions @ VDD = 2.3 to 2.7 V, operation with main clock @ VDD = 2.2 to 2.7 V, operation with main clock MIN. 0.0625 TYP. MAX. 17 Unit MHz
0.0625
13.5
MHz
Preliminary Product Information U15436EJ1V0PM
65
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Recommended Oscillator (1) Main clock oscillator (TA = -40 to +85C) (a) Connection of ceramic resonator or crystal resonator
X1
X2
Parameter Oscillation frequency
Symbol fX (fXX)
Conditions VDD = 2.3 to 2.7 V VDD = 2.2 to 2.7 V
MIN. 2 2
TYP.
MAX. 17 13.5
Unit MHz MHz s s
Oscillation stabilization time
Upon reset release Upon STOP mode release
2 /fX Note
19
Note The TYP. value differs depending on the setting of the oscillation stabilization time select register (OSTS). Caution Ensure that the duty of the oscillation waveform is between 45% and 55%. Remarks 1. Connect the oscillator as close as possible to the X1 and X2 pins. 2. Do not route the wiring near broken lines. 3. For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (b) External clock input
X1
X2 Open
High-speed CMOS inverter External clock
Cautions
1. Connect the high-speed CMOS inverter as close as possible to the X1 pin. 2. Sufficiently evaluate the matching between the V850ES/SA2, V850ES/SA3 and the highspeed CMOS inverter.
66
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2) Subclock oscillator (TA = -40 to +85C) (a) Connection of crystal resonator
XT1
XT2
Parameter Oscillation frequency Oscillation stabilization time
Symbol fXT
Conditions
MIN. 32
TYP. 32.768 10
MAX. 35
Unit kHz s
Caution Ensure that the duty of the oscillation waveform is between 45% and 55%. Remarks 1. Connect the oscillator as close as possible to the XT1 and XT2 pins. 2. Do not route the wiring near broken lines. 3. For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Preliminary Product Information U15436EJ1V0PM
67
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
DC Characteristics (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V) (1/2)
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 Input voltage, low VIL1 VIL2 VIL3 VIL4 VIL5 Output voltage, high VOH1 VOH2 Output voltage, low VOL1 Note 1 Note 2 Note 3 X1 XT1, XT2 Note 1 Note 2 Note 3 X1 XT1, XT2 Note 4 Note 5 Note 4 (Except pins P40 and P42) P40, P42 Note 5 VIN = VDD = EVDD = VDDBU VIN = 0 V VO = VDD = EVDD = VDDBU VO = 0 V IOH = -1 mA IOH = -3 mA IOL = 1.6 mA Conditions MIN. 0.7EVDD T.B.D. 0.7AVDD 0.8VDD 0.8VDDBU EVSS EVSS AVSS VSS VSSBU 0.8EVDD 0.8EVDD 0.4 TYP. MAX. EVDD EVDD AVDD VDD VDDBU 0.3EVDD T.B.D. 0.3AVDD 0.2VDD 0.2VDDBU Unit V V V V V V V V V V
V
V V
VOL2 VOL3 Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low ILIH ILIL ILOH ILOL
IOL = 3 mA IOL = 1.6 mA
0.4 0.4 5 -5 5 -5
V V
A A A A
Notes 1. P21, P31, P90, P91, P94 to P97, P99, P911, P914, PCD1 to PCD3, PCM0 to PCM5, PCS0 to PCS7, PCT0 to PCT7, PDH0 to PDH7, PDL0 to PDL15 (and their alternate-function pins) 2. RESET, P00 to P05, P20, P22, P30, P32, P40 to P46, P92, P93, P98, P910, P912, P913, P915 (and their alternate-function pins) 3. P70 to P715, P80, P81 (and their alternate-function pins) 4. P00 to P05, P20 to P22, P30 to P32, P40 to P46, PCD1 to PCD3, PCM4 to PCM5, PCS4 to PCS7, PCT2, PCT3, PCT5, PCT7 (and their alternate-function pins) 5. P90 to P915, PCM0 to PCM3, PCS0 to PCS3, PCT0, PCT1, PCT4, PCT6, PDH0 to PDH7, PDL0 to PDL15 (and their alternate-function pins)
68
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V) (2/2)
Parameter Supply current Symbol IDD1 Normal operation All peripheral functions operating HALT mode All peripheral functions operating IDLE mode RTC operating Conditions VDD = 2.3 to 2.7 V, fXX = fCLK = 17 MHz fXX = fCLK = 13.5 MHz MIN. TYP. T.B.D. MAX. T.B.D. Unit mA
T.B.D.
T.B.D.
mA
IDD2
VDD = 2.3 to 2.7 V, fXX = fCLK = 17 MHz fXX = fCLK = 13.5 MHz VDD = 2.3 to 2.7 V, fXX = fCLK = 17 MHz fXX = fCLK = 13.5 MHz
T.B.D.
T.B.D.
mA
T.B.D. T.B.D.
T.B.D. T.B.D.
mA mA
IDD3
T.B.D. T.B.D.
T.B.D. T.B.D.
mA
IDD4
STOP mode
Subclock oscillator, RTC operating Subclock oscillator stopped (XT1 = VSS)
A A A A
k
T.B.D.
T.B.D.
IDD5
Backup mode
fXT = 32.768 kHz, RTC operating Subclock oscillation stopped (XT1 = VSS)
T.B.D.
T.B.D.
T.B.D.
T.B.D.
Pull-up resistance
RL
VIN = 0 V
10
30
100
Preliminary Product Information U15436EJ1V0PM
69
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Data Retention Characteristics (1) In STOP mode (TA = -40 to +85C, VSS = AVSS = EVSS = VSSBU = 0 V)
Parameter Data retention voltage Data retention current Symbol VDDDR1 IDDDR1 Conditions STOP mode VDD = AVDD = EVDD = VDDBU = VDDDR1 200 200 0 MIN. 1.8 T.B.D. TYP. MAX. 2.7 T.B.D. Unit V
A s s
ms
Supply voltage rise time Supply voltage fall time Supply voltage hold time (from STOP mode setting) STOP release signal input time Data retention high-level input voltage Data retention low-level input voltage
tRVD1 tFVD1 tHVD1
tDREL1 VIHDR1 VILDR1 All input ports All input ports
0 VIHn 0 VDDDR1 VILn
ms V V
Remark n = 1 to 5
Setting STOP mode
tFVD1
tRVD1
VDD tHVD1 VDDDR1 tDREL1
RESET (input)
VIHDR1
NMI, INTP0 to INTP6 (input)
VIHDR1
NMI, INTP0 to INTP6 (input) (when STOP mode is released at rising edge)
VILDR1
Caution
Shifting to STOP mode and restoring from STOP mode must be performed at VDD = 2.3 V min. (fCLK = 17 MHz) and VDD = 2.2 V min. (fCLK = 13.5 MHz), respectively.
70
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2) In backup mode (TA = -40 to +85C, VSS = AVSS = EVSS = VSSBU = VDD = AVDD = EVDD = 0 V)
Parameter Data retention voltage Data retention current Backup supply voltage rise time Backup supply voltage fall time Mode setting time from RESET to VDD Mode release signal input time from VDD to RESET Symbol VDDDR2 IDDDR2 tRVD2 tFVD2 tHVD2 Conditions Backup mode VDDBU = VDDDR2 T.B.D. T.B.D. T.B.D. MIN. 1.6 T.B.D. TYP. MAX. 2.7 T.B.D. Unit V
A s s
ms
tDREL2
T.B.D.
ms
Caution Shifting to backup mode and restoring from backup mode must be performed at VDD = 2.3 V min. (fCLK = 17 MHz) and VDD = 2.2 V min. (fCLK = 13.5 MHz), respectively.
Setting STOP mode Note VDD, EVDD, AVDD tHVD1 tHVD2 0V tFVD2 VDDBU VDDDR2 tHVD2 tDREL2
0.8EVDD RESET (input) 0.2EVDD
Note Shifting to backup mode and restoring from backup mode must be performed at VDD = 2.3 V min. (fCLK = 17 MHz) and VDD = 2.2 V min. (fCLK = 13.5 MHz), respectively.
Preliminary Product Information U15436EJ1V0PM
71
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
AC Characteristics AC test input measurement points (VDD, AVDD, EVDD, VDDBU)
VDD
VIH Measurement points VIL
VIH VIL
0V
AC test output measurement points
VOH Measurement points VOL
VOH VOL
Load conditions
DUT (Device under test) CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, reduce the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
72
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Clock Timing (1) Operating conditions (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.3 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter X1 input cycle XT1 input cycle X1 input high-level width XT1 input high-level width X1 input low-level width XT1 input low-level width X1 input rise time tXR <4> tWXL <3> tWXH <2> Symbol tCYX <1> Conditions MIN. 58.8 28.5 26.4 12.8 26.4 12.8 0.5 (tCYX - tWXH - tWXL) 0.5 (tCYX - tWXH - tWXL) 58.8 ns 0.5tCYK - 5 0.5tCYK - 5 5 5 16 s ns ns ns ns MAX. Unit ns
s
ns
s
ns
s
ns
X1 input fall time
tXF
<5>
ns
CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time
tCYK tWKH tWKL tKR tKF
<6> <7> <8> <9> <10>
Remark Ensure that the duty for the X1 and XT1 input waveforms is between 45% and 55%. (2) Operating conditions (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter X1 input cycle XT1 input cycle X1 input high-level width XT1 input high-level width X1 input low-level width XT1 input low-level width X1 input rise time X1 input fall time CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time tXR tXF tCYK tWKH tWKL tKR tKF <4> <5> <6> <7> <8> <9> <10> T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. tWXL <3> tWXH <2> Symbol tCYX <1> Conditions MIN. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. ns ns ns ns MAX. Unit ns
s
ns
s
ns
s
ns ns
Remark Ensure that the duty for the X1 and XT1 input waveforms is between 45% and 55%.
Preliminary Product Information U15436EJ1V0PM
73
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Clock timing
<1> <2> <3>
X1, XT1 (input)
<4>
<5> <7>
<6> <8>
CLKOUT (output)
<9>
<10>
74
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Bus Timing (1) Multiplexed bus mode (a) CLKOUT asynchronous: In multiplexed bus mode (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter Address setup time (to ASTB) Address hold time (from ASTB) Delay time from RD to address float Data input setup time from address Data input setup time from RD Delay time from ASTB to RD, WRm Data input hold time (from RD) Address output time from RD Delay time from RD, WRm to ASTB Delay time from RD to ASTB RD, WRm low-level width ASTB high-level width Data output time from WRm Data output setup time (to WRm) Data output hold time (from WRm) WAIT setup time (to address) Symbol tSAST tHSTA tFRDA tSAID tSRID tDSTRDWR tHRDID tDRDA tDRDWRST tDRDST tWRDWRL tWSTH tDWROD tSODWR tHWROD tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time (to ASTB) tSSTWT1 tSSTWT2 WAIT hold time (from ASTB) tHSTWT1 tHSTWT2 HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> <30> <31> <32> <33> <34> <35> <36> <37> <38> n1 n1 n1 n1 n1 n1 n1 n1 nT (1 + n)T T + 10 T - 15 -3 1.5T 0.5T (2n + 7.5)T + 25 1.5T + 25 (0.5 + n)T (1.5 + n)T T - 25 (1 + n)T - 25 (1 + n)T - 20 T - 15 1.5T - 25 (1.5 + n)T - 25 0.5T - 15 0 (1 + i)T - 15 0.5T - 15 (1.5 + i)T - 15 (1 + n)T - 15 T - 15 15 Conditions MIN. 0.5T - 15 0.5T - 15 2 (2 + n)T - 25 (1 + n)T - 25 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. The sampling timing changes when a programmable wait is inserted. 3. m = 0, 1 4. i: Number of idle states inserted after the read cycle (0 or 1). 5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
Preliminary Product Information U15436EJ1V0PM
75
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(b) CLKOUT synchronous: In multiplexed bus mode (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter Delay time from CLKOUT to address tDKA Symbol <39> <40> <41> <42> <43> <44> <45> <46> <47> <48> <49> <50> <51> 15 5 15 5 19 19 Conditions MIN. 0 -12 -12 -5 15 5 19 MAX. 19 7 7 14 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Delay time from CLKOUT to address float tFKA Delay time from CLKOUT to ASTB Delay time from CLKOUT to RD, WRm Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Data output delay time from CLKOUT WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to bus float Delay time from CLKOUT to HLDAK tDKST tDKRDWR tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKF tDKHA
Remarks 1. m = 0, 1 2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
76
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait): In Multiplexed Bus Mode
T1
T2
TW
T3
CLKOUT (output) <39> A16 to A23 (output), A0 to A15 (output) <14> <43> <40> AD0 to AD15 (I/O) Address <41> <12> <11> ASTB (output) <22> <42> <16> <13> <15> <42> <19> <18> <20> <21> <46> Hi-Z Data <41> <17> <44>
RD (output)
<30> <46> <32> <31> <33>
<47>
<47>
WAIT (input) <26> <28> <27> <29>
Remark WR0 and WR1are high level.
Preliminary Product Information U15436EJ1V0PM
77
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait): In Multiplexed Bus Mode
T1
T2
TW
T3
CLKOUT (output) <39> A16 to A23 (output), A0 to A15 (output) <45> AD0 to AD15 (I/O) Address <41> <12> <11> Data <41>
ASTB (output) <22> <42> <16> WR0 (output), WR1 (output) <30> <46> <32> <31> <33> <47> <21> <46> <47> <23> <42> <24> <25> <19>
WAIT (input) <26> <28> <27> <29>
Remark RD is high level.
78
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Bus Hold: In Multiplexed Bus Mode
TH CLKOUT (output) <48> <49>
TH
TH
TI
<48> <34>
HLDRQ (input)
<51> <37> <38>
<51>
HLDAK (output) <35> Hi-Z <36>
<50> A16 to A23 (output)
A0 to A15 (output)
AD0 to AD15 (I/O)
Data
Hi-Z
ASTB (output)
Hi-Z
RD (output), WR0 (output), WR1 (output)
Hi-Z
Preliminary Product Information U15436EJ1V0PM
79
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(2) In separate bus mode (a) Read cycle (CLKOUT asynchronous): In separate bus mode (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter Address setup time (to RD) Address hold time (from RD) RD low-level width Data setup time (to RD) Data hold time (from RD) Data setup time (to address) WAIT setup time (to RD) Symbol tSARD tHARD tWRDL tSISD tHISD tSAID tSRDWT1 tSRDWT2 WAIT hold time (from RD) tHRDWT1 tHRDWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 <52> <53> <54> <55> <56> <57> <58> <59> <60> <61> <62> <63> <64> <65> T (1 + n) T 0.5T (0.5 + n) T T - 20 (1 + n) T - 20 Conditions MIN. 0.5T - 15 2 (1.5 + n) T - 10 20 0 (2 + n) T - 25 0.5T - 20 (0.5 + n) T - 20 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency) 2. n: Number of wait clocks inserted in bus cycle The sampling timing changes when a programmable wait is inserted. 3. The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from X1. (b) Read cycle (CLKOUT synchronous): In separate bus mode (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter Symbol <66> <67> <68> <69> <70> <71> Conditions MIN. 0 15 5 0 15 5 19 MAX. 19 Unit ns ns ns ns ns ns
Delay time from CLKOUT to address, CS tDKSA Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to RD WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tSISDK tHKISD tDKSR tSWTK tHKWT
Remark The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from X1.
80
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
(c) Write cycle (CLKOUT asynchronous): In separate bus mode (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter Address setup time (to WRm) Address hold time (from WRm) WRm low-level width Data output time from WRm Data setup time (to WRm) Data hold time (from WRm) Data setup time (to address) WAIT setup time (to WRm) Symbol tSAW tHAW tWWRL tDOSDW tSOSDW tHOSDW tSAOD tSWRWT1 tSWRWT2 WAIT hold time (from WRm) tHWRWT1 tHWRWT2 WAIT setup time (to address) tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 <72> <73> <74> <75> <76> <77> <78> <79> <80> <81> <82> <83> <84> <85> <86> T (1 + n) T Conditions MIN. T - 15 0.5T - 10 (0.5 + n) T - 10 -5 (0.5 + n) T - 10 0.5T - 10 T - 25 20 nT - 20 0 nT T - 20 (1 + n) T - 20 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. m = 0, 1 2. T = 1/fCPU (fCPU: CPU operation clock frequency) 3. n: Number of wait clocks inserted in bus cycle The sampling timing changes when a programmable wait is inserted. 4. The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from X1. (d) Write cycle (CLKOUT synchronous): In separate bus mode (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter Symbol <87> <88> <89> <90> <91> Conditions MIN. 0 0 0 15 5 MAX. 19 19 19 Unit ns ns ns ns ns
Delay time from CLKOUT to address, CS tDKSA Delay time from CLKOUT to data output Delay time from CLKOUT to WRm WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) tDKSD tDKSW tSWTK tHKWT
Remarks 1. m = 0, 1 2. The values in the above specifications are the values for when clocks with a 1:1 duty ratio are input from X1.
Preliminary Product Information U15436EJ1V0PM
81
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Read Cycle (CLKOUT Asynchronous, 1 Wait): In Separate Bus Mode
T1
TW
T2
CLKOUT (output)
CS0 to CS3 (output) A0 to A23 (output) <53> <57> AD0 to AD15 (I/O) Hi-Z <56> <55> <54> RD (output) <61> <59> <60> <58> WAIT (input) <62> <64> <63> <65> Hi-Z
<52>
82
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Read Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode
T1
TW
T2
CLKOUT (output) <66>
<66> CS0 to CS3 (output) A0 to A23 (output) <67> Hi-Z
<68> Hi-Z <69>
AD0 to AD15 (I/O)
<69>
RD (output) <70> <71> <70> <71>
WAIT (input)
Preliminary Product Information U15436EJ1V0PM
83
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Write Cycle (CLKOUT Asynchronous, 1 Wait): In Separate Bus Mode
T1
TW
T2
CLKOUT (output)
CS0 to CS3 (output) A0 to A23 (output) <73> <78> AD0 to AD15 (I/O) Hi-Z <75> <72> <77> <76> <74> WR0, WR1 (output) <82> <80> <79> <81> WAIT (input) <83> <85> <84> <86> Hi-Z
84
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Write Cycle (CLKOUT Synchronous, 1 Wait): In Separate Bus Mode
T1
TW
T2
CLKOUT (output) <87> <87>
CS0 to CS3 (output) A0 to A23 (output) <88> Hi-Z <88> Hi-Z
AD0 to AD15 (I/O)
<89>
<89>
WR0, WR1 (output)
<90>
<91>
<90>
<91>
WAIT (input)
Preliminary Product Information U15436EJ1V0PM
85
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Reset/Interrupt Timing (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter RESET high-level width RESET low-level width NMI high-level width NMI low-level width INTPn high-level width Symbol tWRSH tWRSL tWNIH tWNIL tWITH <92> <93> <94> <95> <96> n = 0 to 6 (analog noise elimination) n = 0 to 6 (analog noise elimination) Conditions MIN. 500 500 500 500 500 MAX. Unit ns ns ns ns ns
INTPn low-level width
tWITL
<97>
500
ns
Remark T = 1/fXX Reset
<92>
<93>
RESET (input)
Interrupt
<94>
<95>
NMI (input)
<96>
<97>
INTPn (input)
Remark n = 0 to 6
86
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Timer Timing (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter TIn high-level width Symbol Conditions n = 0, 1 n = 2 to 5 TIn low-level width n = 0, 1 n = 2 to 5 TCLRn high-level width TCLRn low-level width INTPnm high-level width INTPnm low-level width tWITH tWITL n = 0, 1 n = 0, 1 nm = 00, 01, 10, 11 nm = 00, 01, 10, 11 MIN. 2T + 20 40 2T + 20 40 2T + 20 2T + 20 2T + 20 2T + 20 MAX. Unit ns ns ns ns ns ns ns ns
Remark T = 1/fXX
Preliminary Product Information U15436EJ1V0PM
87
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
CSI Timing (1) Master mode (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter SCKn cycle time SCKn high-/low-level width Symbol tKCY1 tKH1, tKL1 tSIK1 tKSI1 tKSO1 <98> <99> Output Output Conditions MIN. 200 tKCY1/2 - 10 MAX. Unit ns ns
SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output
<100> <101> <102>
30 30 30
ns ns ns
Remark n = 0 to 3 (V850ES/SA2), n = 0 to 4 (V850ES/SA3) (2) Slave mode (TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V, CL = 50 pF)
Parameter SCKn cycle time SCKn high-/low-level width Symbol tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2 <98> <99> Output Output Conditions MIN. 200 90 MAX. Unit ns ns
SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output
<100> <101> <102>
50 50 50
ns ns ns
Remark n = 0 to 3 (V850ES/SA2), n = 0 to 4 (V850ES/SA3)
<98> <99> SCKn (I/O) <99>
<100> Hi-Z
<101> Hi-Z
SIn (input)
Input data
<102>
SOn (output)
Output data
Remark n = 0 to 3 (V850ES/SA2), n = 0 to 4 (V850ES/SA3)
88
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
I C Bus Mode (PD703201Y, 703204Y, 70F3201Y, 70F3204Y only)
2
(TA = -40 to +85C, VDD = AVDD = EVDD = VDDBU = 2.2 to 2.7 V, VSS = AVSS = EVSS = VSSBU = 0 V)
Parameter Symbol Normal Mode MIN. SCL clock frequency Bus-free time (between stop/start conditions) Hold timeNote 1 SCL clock low-level width SCL clock high-level width Setup time for start/restart conditions Data hold time CBUS compatible master I2C mode Data setup time SDA and SCL signal rise time SDA and SCL signal fall time Stop condition setup time Pulse width with spike suppressed by input filter Capacitance load of each bus line tSU:DAT tR tF tSU:STO tSP <109> <110> <111> <112> <113> fCLK tBUF <103> 0 4.7 MAX. 100 - High-Speed Mode MIN. 0 1.3 MAX. 400 - kHz Unit
s s s s s s
tHD:STA tLOW tHIGH tSU:STA
<104> <105> <106> <107>
4.0 4.7 4.0 4.7
- - - -
0.6 1.3 0.6 0.6
- - - -
tHD:DAT
<108>
5.0
-
-
-
0Note 2 250 - - 4.0 -
- - 1,000 300 - -
0Note 2 100
Note 4
0.9Note 3 -
Note 5
s
ns ns ns
20 + 0.1Cb
300 300 - 50
20 + 0.1Cb 0.6 0
Note 5
s
ns
Cb
-
400
-
400
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time. 2. The system requires a minimum of 300 ns hold time internally for the SDA signal (at VIHmin.. of SCL signal) in order to occupy the undefined area at the falling edge of SCL. 3. If the system does not extend the SCL signal low hold time (tLOW), only the maximum data hold time (tHD:
DAT)
needs to be satisfied.
2 2 2
4. The high-speed-mode I C bus can be used in a normal-mode I C bus system. In this case, set the highspeed-mode I C bus so that it meets the following conditions. * If the system does not extend the SCL signal's low state hold time: tSU:DAT 250 ns * If the system extends the SCL signal's low state hold time: Transmit the following data bit to the SDA line prior to releasing the SCL line (tRmax. + tSU:DAT = 1,000 + 250 = 1,250 ns: Normal mode I C bus specification). 5. Cb: Total capacitance of one bus line (unit: pF)
2
Preliminary Product Information U15436EJ1V0PM
89
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
I C Bus Mode (PD703201Y, 703204Y, 70F3201Y, 70F3204Y only)
2
<105> <106> SCL (I/O) <111> <110> <104> <108> <109> <107> <104> <113> <112>
SDA (I/O) <103> Stop condition Start condition <110> <111> Restart condition Stop condition
A/D Converter (TA = -40 to +85C, VDD = AVDD = AVREF0 = 2.2 to 2.7 V, AVSS = VSS = 0 V, CL = 50 pF)
Parameter Resolution Overall error
Note 1
Symbol
Conditions
MIN. 10
TYP. 10
MAX. 10 T.B.D.
Unit bit %FSR
Conversion time Zero-scale error
Note 1
tCONV
T.B.D. T.B.D. T.B.D.
s
%FSR %FSR LSB LSB V V
Full-scale error Note 1 Integral linearity error
Note 2
T.B.D. T.B.D. AVREF VIAN AIREF0 AIDD AVREF0 = AVDD 2.2 AVSS T.B.D. T.B.D. 2.7 AVREF
Differential linearity error
Note 2
Analog reference voltage Analog input voltage AVREF0 current AVDD power supply current
A
mA
Notes 1. Excluding quantization error (0.05 %FSR) 2. Excluding quantization error (0.5 LSB) Remark LSB: Least Significant Bit FSR: Full Scale Range
90
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
D/A Converter (TA = -40 to +85C, VDD = AVDD = AVREF1 = 2.2 to 2.7 V, AVSS = VSS = 0 V, CL = 50 pF)
Parameter Resolution Overall error
Note
Symbol
Conditions
MIN. 8
TYP. 8
MAX. 8 T.B.D.
Unit bit %FSR
Load conditions: 2 M, 30 pF AVREF1 = VDD
Settling time Output resistance Analog reference voltage AVREF1 current AVREF AVREF1 AVREF1 = VDD Per channel 2.2 T.B.D. T.B.D.
T.B.D.
s
k
2.7
V mA
Note Excludes quantization error (0.05%FSR).
Preliminary Product Information U15436EJ1V0PM
91
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
21. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P H I
M
J K S
N
S L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX.
S100GC-50-8EU, 8EA-2
92
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
121-PIN PLASTIC FBGA (12x12)
E
w
SB
ZD
ZE
B
A D
13 12 11 10 9 8 7 6 5 4 3 2 1 NM L K J HG F E DC B A
INDEX MARK
w
SA
A y1 S A2 S
y
S
b
e
A1
x
M
S AB
ITEM D E w A A1 A2 e b x y y1 ZD ZE MILLIMETERS 12.000.10 12.000.10 0.20 1.480.10 0.350.06 1.13 0.80 0.50 +0.05 -0.10 0.08 0.10 0.20 1.20 1.20 P121F1-80-EA6
Preliminary Product Information U15436EJ1V0PM
93
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
APPENDIX DEVELOPMENT TOOLS
(1) Hardware
Product Name In-circuit emulator IE-V850ES-xx (provisional name) IE-703204-MC-EM1Note (provisional name)
Note
Description In-circuit emulator for V850ES
In-circuit emulator option board
Option board to emulate V850ES/SA2, V850ES/SA3 peripheral functions in combination with in-circuit emulator Emulation probe for 100-pin LQFP Emulation probe for 121-pin FBGA Power supply for in-circuit emulator Interface board for connection to PC (for PCMCIA) Interface board for connection to PC (for PCI) Flash programmer for writing a program to a singlepower-supply flash memory product. Program adapter for 100-pin LQFP Program adapter for 121-pin FBGA
Emulation probe
V850ES/SA2 V850ES/SA3
Note Note IE-70000-MC-PS-B IE-70000-CD-IF-A IE-70000-PCI-IF
Power supply unit PC interface board
Flash programmer
Note
Program adapter
V850ES/SA2 V850ES/SA3
Note Note
Note Under development (2) Software
Product Name Compiler Debugger CA850 ID850 Description C compiler compliant with ANSI-C Debugger used in combination with in-circuit emulator Real-time OS compliant with ITRON specifications Definition file for V850ES/SA2 Definition file for V850ES/SA3
Real-time OS Device file V850ES/SA2 V850ES/SA3
RX850 DF703201Note DF703204
Note
Note Under development
94
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
[MEMO]
Preliminary Product Information U15436EJ1V0PM
95
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Caution
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C system, provided that the system conforms to the I C Standard Specification as defined by Philips.
2 2
2
2
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V850 Family, V850ES/SA2, and V850ES/SA3 are trademarks of NEC Corporation. TRON stands for The Real-time Operating system Nucleus. ITRON is an abbreviation of Industrial TRON.
96
Preliminary Product Information U15436EJ1V0PM
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Preliminary Product Information U15436EJ1V0PM
97
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed: PD70F3201, 70F3201Y, 70F3204, 70F3204Y The customer must judge the need for license: PD703201, 703201Y, 703204, 703204Y
* The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M5 98. 8

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